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Searched refs:SchedWrite (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZSchedule.td15 def NormalGr : SchedWrite;
16 def Cracked : SchedWrite;
17 def GroupAlone : SchedWrite;
18 def BeginGroup : SchedWrite;
19 def EndGroup : SchedWrite;
21 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
22 def LSULatency : SchedWrite;
25 foreach L = 1 - 30 in def "WLat"#L : SchedWrite;
28 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
38 def "FXa"#Num : SchedWrite;
[all …]
DSystemZScheduleZ13.td63 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
87 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
89 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
90 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
91 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
92 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
93 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
94 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
95 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
DSystemZScheduleZ14.td63 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
87 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
89 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
90 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
91 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
92 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
93 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
94 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
95 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
DSystemZScheduleZ196.td63 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
81 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
82 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
83 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
84 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
DSystemZScheduleZEC12.td63 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
82 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
83 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
84 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
85 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64Schedule.td21 def WriteImm : SchedWrite; // MOVN, MOVZ
25 def WriteI : SchedWrite; // ALU
26 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
27 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
33 def WriteIS : SchedWrite; // Shift/Scale
34 def WriteID32 : SchedWrite; // 32-bit Divide
35 def WriteID64 : SchedWrite; // 64-bit Divide
37 def WriteIM32 : SchedWrite; // 32-bit Multiply
38 def WriteIM64 : SchedWrite; // 64-bit Multiply
[all …]
DAArch64SchedThunderX.td45 // Subtarget-specific SchedWrite types mapping the ProcResources and
DAArch64SchedA53.td50 // Subtarget-specific SchedWrite types which both map the ProcResources and
/external/llvm/lib/Target/AArch64/
DAArch64Schedule.td21 def WriteImm : SchedWrite; // MOVN, MOVZ
25 def WriteI : SchedWrite; // ALU
26 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
27 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
33 def WriteIS : SchedWrite; // Shift/Scale
34 def WriteID32 : SchedWrite; // 32-bit Divide
35 def WriteID64 : SchedWrite; // 64-bit Divide
37 def WriteIM32 : SchedWrite; // 32-bit Multiply
38 def WriteIM64 : SchedWrite; // 64-bit Multiply
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86Schedule.td20 def WriteRMW : SchedWrite;
22 // Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
23 multiclass X86WriteRes<SchedWrite SchedRW,
33 // Most instructions can fold loads, so almost every SchedWrite comes in two
35 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
37 class X86FoldableSchedWrite : SchedWrite {
38 // The SchedWrite to use when a load is folded into the instruction.
39 SchedWrite Folded;
45 def Ld : SchedWrite;
48 let Folded = !cast<SchedWrite>(NAME#"Ld");
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
61 def WriteALU : SchedWrite;
65 def WriteALUsi : SchedWrite; // Shift by immediate.
66 def WriteALUsr : SchedWrite; // Shift by register.
67 def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
71 def WriteCMP : SchedWrite;
72 def WriteCMPsi : SchedWrite;
73 def WriteCMPsr : SchedWrite;
76 def WriteMUL16 : SchedWrite; // 16-bit multiply.
77 def WriteMUL32 : SchedWrite; // 32-bit multiply.
[all …]
DARMScheduleA9.td2087 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2089 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2152 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2157 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2187 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2192 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
/external/llvm/lib/Target/AMDGPU/
DSISchedule.td20 def WriteBranch : SchedWrite;
21 def WriteExport : SchedWrite;
22 def WriteLDS : SchedWrite;
23 def WriteSALU : SchedWrite;
24 def WriteSMEM : SchedWrite;
25 def WriteVMEM : SchedWrite;
26 def WriteBarrier : SchedWrite;
29 def Write32Bit : SchedWrite;
30 def WriteQuarterRate32 : SchedWrite;
31 def WriteFullOrQuarterRate32 : SchedWrite;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSISchedule.td20 def WriteBranch : SchedWrite;
21 def WriteExport : SchedWrite;
22 def WriteLDS : SchedWrite;
23 def WriteSALU : SchedWrite;
24 def WriteSMEM : SchedWrite;
25 def WriteVMEM : SchedWrite;
26 def WriteBarrier : SchedWrite;
29 def Write32Bit : SchedWrite;
30 def WriteQuarterRate32 : SchedWrite;
31 def WriteFullOrQuarterRate32 : SchedWrite;
[all …]
/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
58 def WriteALU : SchedWrite;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
64 def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
68 def WriteCMP : SchedWrite;
69 def WriteCMPsi : SchedWrite;
70 def WriteCMPsr : SchedWrite;
73 def WriteDiv : SchedWrite;
76 def WriteLd : SchedWrite;
[all …]
DARMScheduleA9.td2063 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2065 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2128 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2133 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2163 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2168 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
/external/llvm/lib/Target/Lanai/
DLanaiSchedule.td58 def WriteLD : SchedWrite;
59 def WriteST : SchedWrite;
60 def WriteLDSW : SchedWrite;
61 def WriteSTSW : SchedWrite;
62 def WriteALU : SchedWrite;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiSchedule.td58 def WriteLD : SchedWrite;
59 def WriteST : SchedWrite;
60 def WriteLDSW : SchedWrite;
61 def WriteSTSW : SchedWrite;
62 def WriteALU : SchedWrite;
/external/llvm/include/llvm/Target/
DTargetSchedule.td209 // instruction. One SchedWrite type must be listed for each explicit
210 // def operand in order. Additional SchedWrite types may optionally be
217 // single SchedWrite and single SchedRead in any order.
223 class SchedWrite : SchedReadWrite;
224 def NoWrite : SchedWrite;
229 // Define a SchedWrite that is modeled as a sequence of other
239 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
240 list<SchedWrite> Writes = writes;
261 // Define the resources and latency of a SchedWrite. This will be used
263 // SchedWrite is defined by the target, while WriteResources is
[all …]
/external/llvm/lib/Target/X86/
DX86Schedule.td21 def WriteRMW : SchedWrite;
23 // Most instructions can fold loads, so almost every SchedWrite comes in two
25 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
27 class X86FoldableSchedWrite : SchedWrite {
28 // The SchedWrite to use when a load is folded into the instruction.
29 SchedWrite Folded;
35 def Ld : SchedWrite;
38 let Folded = !cast<SchedWrite>(NAME#"Ld");
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td215 // instruction. One SchedWrite type must be listed for each explicit
216 // def operand in order. Additional SchedWrite types may optionally be
223 // single SchedWrite and single SchedRead in any order.
229 class SchedWrite : SchedReadWrite;
230 def NoWrite : SchedWrite;
235 // Define a SchedWrite that is modeled as a sequence of other
245 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
246 list<SchedWrite> Writes = writes;
270 // Define the resources and latency of a SchedWrite. This will be used
272 // SchedWrite is defined by the target, while WriteResources is
[all …]
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp93 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
649 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
653 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
654 return SchedWrite.TheDef; in FindWriteResources()
657 for (Record *A : SchedWrite.Aliases) { in FindWriteResources()
680 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
694 + SchedWrite.TheDef->getName()); in FindWriteResources()
DCodeGenSchedule.cpp424 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); in expandRWSeqForProc() local
426 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end(); in expandRWSeqForProc()
445 if (!SchedWrite.IsSequence) { in expandRWSeqForProc()
450 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc()
452 for (IdxIter I = SchedWrite.Sequence.begin(), E = SchedWrite.Sequence.end(); in expandRWSeqForProc()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp104 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
837 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
841 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
842 return SchedWrite.TheDef; in FindWriteResources()
845 for (Record *A : SchedWrite.Aliases) { in FindWriteResources()
868 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
882 SchedWrite.TheDef->getName()); in FindWriteResources()
DCodeGenSchedule.cpp534 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); in expandRWSeqForProc() local
536 for (const Record *Rec : SchedWrite.Aliases) { in expandRWSeqForProc()
554 if (!SchedWrite.IsSequence) { in expandRWSeqForProc()
559 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc()
561 for (unsigned Idx : SchedWrite.Sequence) { in expandRWSeqForProc()

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