Home
last modified time | relevance | path

Searched refs:Src2 (Results 1 – 25 of 55) sorted by relevance

123

/external/swiftshader/third_party/LLVM/lib/ExecutionEngine/Interpreter/
DExecution.cpp50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
54 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
65 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
76 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
87 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
98 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
124 (void*)(intptr_t)Src2.PointerVal); \
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
56 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
67 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
78 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
89 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
100 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
56 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
67 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
78 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
89 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
100 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp71 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink() local
78 if (Src2) { in canShrink()
95 if (!Src2->isReg() || !TRI.isVGPR(MRI, Src2->getReg()) || in canShrink()
450 const MachineOperand *Src2 = in runOnMachineFunction() local
452 if (!Src2->isReg()) in runOnMachineFunction()
454 unsigned SReg = Src2->getReg(); in runOnMachineFunction()
468 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction() local
480 if (Src2 && Src2->getReg() != AMDGPU::VCC) { in runOnMachineFunction()
481 if (TargetRegisterInfo::isVirtualRegister(Src2->getReg())) in runOnMachineFunction()
482 MRI.setRegAllocationHint(Src2->getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
[all …]
DAMDGPUMacroFusion.cpp45 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
47 return FirstMI->definesRegister(Src2->getReg()); in shouldScheduleAdjacent()
DSIOptimizeExecMasking.cpp106 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
107 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
DSIPeepholeSDWA.cpp648 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in matchSDWAOperand() local
649 auto Width = foldToImm(*Src2); in matchSDWAOperand()
968 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in convertToSDWA() local
969 assert(Src2); in convertToSDWA()
970 SDWAInst.add(*Src2); in convertToSDWA()
/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp84 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink() local
91 if (Src2) { in canShrink()
96 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
348 const MachineOperand *Src2 = in runOnMachineFunction() local
350 if (!Src2->isReg()) in runOnMachineFunction()
352 unsigned SReg = Src2->getReg(); in runOnMachineFunction()
386 const MachineOperand *Src2 = in runOnMachineFunction() local
388 if (Src2) { in runOnMachineFunction()
391 Inst32.addOperand(*Src2); in runOnMachineFunction()
396 copyFlagsToImplicitVCC(*Inst32, *Src2); in runOnMachineFunction()
DSIInstrInfo.cpp1241 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); in FoldImmediate() local
1249 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
1289 if (Src2->isReg() && Src2->getReg() == Reg) { in FoldImmediate()
1316 Src2->ChangeToImmediate(Imm); in FoldImmediate()
1435 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in convertToThreeAddress() local
1444 .addOperand(*Src2) in convertToThreeAddress()
1762 const MachineOperand &Src2 = MI.getOperand(Src2Idx); in verifyInstruction() local
1763 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { in verifyInstruction()
1765 !compareMachineOp(Src0, Src2)) { in verifyInstruction()
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp97 const MachineOperand &Src2) const;
176 const MachineOperand &Src2) const { in getMuxOpcode()
177 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
185 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
266 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
268 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; in genMuxInBlock()
284 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
285 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
DHexagonPeephole.cpp160 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
177 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
178 if (Src2.getImm() != 32) in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp136 const MachineOperand &Src2) const;
210 const MachineOperand &Src2) const { in getMuxOpcode()
211 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
219 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
306 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
308 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; in genMuxInBlock()
324 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
325 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
DHexagonPeephole.cpp158 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
162 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
175 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
176 if (Src2.getImm() != 32) in runOnMachineFunction()
DHexagonConstPropagation.cpp1857 const MachineOperand &Src2, const CellMap &Inputs, bool &Result);
2566 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexCompare() local
2570 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result); in evaluateHexCompare()
2588 const MachineOperand &Src1, const MachineOperand &Src2, in evaluateHexCompare2() argument
2591 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2()
2592 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2()
2596 Register R2(Src2); in evaluateHexCompare2()
2599 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2605 Register R2(Src2); in evaluateHexCompare2()
2609 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp147 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
159 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
162 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
182 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
187 SDValue CCReg = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
232 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
235 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
DSystemZSelectionDAGInfo.h41 SDValue Src1, SDValue Src2, SDValue Size,
57 SDValue Src1, SDValue Src2,
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp150 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
162 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
165 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
185 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
190 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
236 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
239 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
DSystemZSelectionDAGInfo.h41 SDValue Src1, SDValue Src2, SDValue Size,
57 SDValue Src1, SDValue Src2,
DSystemZISelLowering.cpp3220 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_OP() local
3227 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_OP()
3229 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType()); in lowerATOMIC_LOAD_OP()
3253 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
3257 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
3262 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3287 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_SUB() local
3289 SDLoc DL(Src2); in lowerATOMIC_LOAD_SUB()
3291 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_SUB()
3300 Src2); in lowerATOMIC_LOAD_SUB()
[all …]
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp378 const MachineOperand &Src2 = MI.getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM() local
382 .addOperand(Src2); in processInstructionForSLM()
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp164 unsigned Src0, Src1, Src2; in TEST() local
183 m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2))); in TEST()
187 ASSERT_EQ(Src2, Copies[2]); in TEST()
/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp130 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
137 Inst.addOperand(Src2); in EmitBinary()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp128 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
135 Inst.addOperand(Src2); in EmitBinary()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineCalls.cpp1477 const APFloat &Src2) { in fmed3AMDGCN() argument
1478 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
1483 return maxnum(Src1, Src2); in fmed3AMDGCN()
1488 return maxnum(Src0, Src2); in fmed3AMDGCN()
3453 Value *Src2 = II->getArgOperand(2); in visitCallInst() local
3460 NewCall = Builder.CreateMinNum(Src1, Src2); in visitCallInst()
3462 NewCall = Builder.CreateMinNum(Src0, Src2); in visitCallInst()
3463 } else if (match(Src2, m_NaN()) || isa<UndefValue>(Src2)) { in visitCallInst()
3482 if (isa<Constant>(Src1) && !isa<Constant>(Src2)) { in visitCallInst()
3483 std::swap(Src1, Src2); in visitCallInst()
[all …]
/external/swiftshader/third_party/subzero/src/
DIceTargetLowering.h588 auto *Src2 = thunk2(); in applyToThunkedArgs() local
589 return insertScalarInstruction(Res, Src0, Src1, Src2); in applyToThunkedArgs()

123