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Searched refs:SubRegIndex (Results 1 – 25 of 67) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DConcatenatedSubregs.td22 def sub0 : SubRegIndex<32>;
23 def sub1 : SubRegIndex<32, 32>;
24 def sub2 : SubRegIndex<32, 64>;
26 def ssub0 : SubRegIndex<16>;
27 def ssub1 : SubRegIndex<16, 16>;
91 // CHECK-LABEL: SubRegIndex sub0:
92 // CHECK-LABEL: SubRegIndex sub1:
93 // CHECK-LABEL: SubRegIndex sub2:
95 // CHECK: SubRegIndex ssub1_ssub2:
96 // CHECK: SubRegIndex ssub3_ssub4:
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMRegisterInfo.td29 def ssub_0 : SubRegIndex;
30 def ssub_1 : SubRegIndex;
31 def ssub_2 : SubRegIndex; // In a Q reg.
32 def ssub_3 : SubRegIndex;
34 def dsub_0 : SubRegIndex;
35 def dsub_1 : SubRegIndex;
36 def dsub_2 : SubRegIndex;
37 def dsub_3 : SubRegIndex;
38 def dsub_4 : SubRegIndex;
39 def dsub_5 : SubRegIndex;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp223 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
224 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
225 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
238 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
239 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIInstructions.td748 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
751 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
755 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
758 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
764 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
767 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
771 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
774 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
780 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
783 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
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DAMDGPURegisterInfo.td17 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
DSIRegisterInfo.td15 list<SubRegIndex> ret2 = [sub0, sub1];
16 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
17 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
18 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
19 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3,
24 list<SubRegIndex> ret = !if(!eq(size, 2), ret2,
263 list<SubRegIndex> indices = getSubRegs<size>.ret,
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
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/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
301 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DAMDGPURegisterInfo.td17 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
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/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCQPXLoadSplat.cpp108 unsigned SubRegIndex = in runOnMachineFunction() local
110 unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); in runOnMachineFunction()
DPPCRegisterInfo.td14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
/external/llvm/lib/Target/PowerPC/
DPPCQPXLoadSplat.cpp108 unsigned SubRegIndex = in runOnMachineFunction() local
110 unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); in runOnMachineFunction()
DPPCRegisterInfo.td14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
20 def sub_128 : SubRegIndex<128>;
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td30 def qqsub_0 : SubRegIndex<256>;
31 def qqsub_1 : SubRegIndex<256, 256>;
34 def qsub_0 : SubRegIndex<128>;
35 def qsub_1 : SubRegIndex<128, 128>;
39 def dsub_0 : SubRegIndex<64>;
40 def dsub_1 : SubRegIndex<64, 64>;
48 def ssub_0 : SubRegIndex<32>;
49 def ssub_1 : SubRegIndex<32, 32>;
53 def gsub_0 : SubRegIndex<32>;
54 def gsub_1 : SubRegIndex<32, 32>;
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMRegisterInfo.td32 def qqsub_0 : SubRegIndex<256>;
33 def qqsub_1 : SubRegIndex<256, 256>;
36 def qsub_0 : SubRegIndex<128>;
37 def qsub_1 : SubRegIndex<128, 128>;
41 def dsub_0 : SubRegIndex<64>;
42 def dsub_1 : SubRegIndex<64, 64>;
50 def ssub_0 : SubRegIndex<32>;
51 def ssub_1 : SubRegIndex<32, 32>;
65 def gsub_0 : SubRegIndex<32>;
66 def gsub_1 : SubRegIndex<32, 32>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZRegisterInfo.td57 def subreg_32bit : SubRegIndex;
58 def subreg_odd32 : SubRegIndex;
59 def subreg_even : SubRegIndex;
60 def subreg_odd : SubRegIndex;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td22 def sub_8bit : SubRegIndex;
23 def sub_8bit_hi : SubRegIndex;
24 def sub_16bit : SubRegIndex;
25 def sub_32bit : SubRegIndex;
27 def sub_ss : SubRegIndex;
28 def sub_sd : SubRegIndex;
29 def sub_xmm : SubRegIndex;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td14 def sub_lt : SubRegIndex;
15 def sub_gt : SubRegIndex;
16 def sub_eq : SubRegIndex;
17 def sub_un : SubRegIndex;
18 def sub_32 : SubRegIndex;
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.td19 def lo16 : SubRegIndex;
20 def hi16 : SubRegIndex;
21 def lo32 : SubRegIndex;
22 def hi32 : SubRegIndex;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td24 def sub_8bit : SubRegIndex<8>;
25 def sub_8bit_hi : SubRegIndex<8, 8>;
26 def sub_8bit_hi_phony : SubRegIndex<8, 8>;
27 def sub_16bit : SubRegIndex<16>;
28 def sub_16bit_hi : SubRegIndex<16, 16>;
29 def sub_32bit : SubRegIndex<32>;
30 def sub_xmm : SubRegIndex<128>;
31 def sub_ymm : SubRegIndex<256>;

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