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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dmisched-int-basic.mir61 # CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc,…
123 %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
/external/llvm/test/MC/ARM/
Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
/external/llvm/lib/Target/ARM/
DARMISelLowering.h166 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
DARMScheduleSwift.td291 (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
DARMISelDAGToDAG.cpp2945 case ARMISD::UMLAL:{ in Select()
2990 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
DARMInstrInfo.td3944 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3975 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
5780 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5794 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
DARMISelLowering.cpp1219 case ARMISD::UMLAL: return "ARMISD::UMLAL"; in getTargetNodeName()
8891 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
8979 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
8982 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc223 TmpInst.setOpcode(ARM::UMLAL);
DARMGenAsmWriter.inc1441 96990U, // UMLAL
4661 0U, // UMLAL
7102 // SMLAL, UMLAL
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h200 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
DARMScheduleSwift.td308 (instregex "SMLAL", "UMLAL", "SMLALBT",
DARMScheduleR52.td280 "SMLAL", "UMLAL", "SMLALBT",
DARMISelDAGToDAG.cpp2817 case ARMISD::UMLAL:{ in Select()
2831 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
DARMInstrInfo.td4125 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4159 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
6096 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6110 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
DARMISelLowering.cpp1348 case ARMISD::UMLAL: return "ARMISD::UMLAL"; in getTargetNodeName()
10144 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
10251 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
10254 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
12755 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
DARMScheduleA9.td2552 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
/external/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td523 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td525 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3877 ### UMLAL ### subsection
3887 ### UMLAL ### subsection
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc511 92184U, // UMLAL
3304 0U, // UMLAL
6181 // SMLAL, UMLAL
9214 // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2115 # UMLAL
Dthumb2.txt2277 # UMLAL
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2288 # UMLAL
Dthumb2.txt2428 # UMLAL

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