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Searched refs:V60 (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h42 V4, V5, V55, V60 enumerator
94 bool hasV60TOps() const { return getHexagonArchVersion() >= V60; } in hasV60TOps()
95 bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; } in hasV60TOpsOnly()
DHexagonSchedule.td20 // V60 Machine Info -
DHexagonScheduleV60.td61 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
78 // in the CVI co-processor in the Hexagon V60 machine.
310 // Hexagon V60 Resource Definitions -
DHexagonSubtarget.cpp74 { "hexagonv60", V60 }, in initializeSubtargetDependencies()
DHexagon.td28 def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">;
DHexagonRegisterInfo.cpp127 case HexagonSubtarget::V60: in getCalleeSavedRegs()
DHexagonInstrFormats.td441 // V60 Instruction Format Definitions +
447 // V60 Instruction Format Definitions +
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonScheduleV60.td11 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
28 // in the CVI co-processor in the Hexagon V60 machine.
80 // Hexagon V60 Resource Definitions -
DHexagonDepArch.td17 …btargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architec…
DHexagonDepArch.h18 enum class ArchEnum { V4,V5,V55,V60,V62,V65 }; enumerator
DHexagonSubtarget.h136 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60; in hasV60Ops()
139 return getHexagonArchVersion() == Hexagon::ArchEnum::V60; in hasV60OpsOnly()
DHexagonInstrFormatsV60.td10 // This file describes the Hexagon V60 instruction classes in TableGen format.
DHexagonInstrFormatsV65.td10 // This file describes the Hexagon V60 instruction classes in TableGen format.
DHexagonSchedule.td69 // V60 Machine Info -
DHexagonSubtarget.cpp95 {"generic", Hexagon::ArchEnum::V60}, in initializeSubtargetDependencies()
99 {"hexagonv60", Hexagon::ArchEnum::V60}, in initializeSubtargetDependencies()
DHexagon.td29 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
31 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
DHexagonRegisterInfo.cpp125 case Hexagon::ArchEnum::V60: in getCalleeSavedRegs()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dbug20416.s1 … -triple=hexagon -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
11 # CHECK-V60-ERROR: rror: invalid instruction packet: slot error
Delf-flags.s4 … %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V60 %s
10 # CHECK-V60: Flags: 0x60
/external/llvm/test/MC/Hexagon/
Delf-flags.s4 … %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V60 %s
9 # CHECK-V60: Flags: 0x60
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dnv_store_vec.ll3 ; Check that we generate new value stores in V60.
Dswp-vsum.ll11 ; V60 does not pipeline due to latencies.
Dpred-taken-jump.ll3 ; Predicated (old) taken jumps weren't supported prior to V60. The purpose
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCTargetDesc.cpp82 clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
284 case Hexagon::ArchEnum::V60: in selectHexagonFS()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dx86-vec_demanded_elts.ll42 ; CHECK-NEXT: [[V60:%.*]] = insertelement <2 x double> undef, double %d, i32 0
43 ; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V60]])

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