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Searched refs:VCGE (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvfcmp.ll28 ; ole is implemented with VCGE
63 ; ugt is implemented with VCGE/VMVN
75 ; ult is implemented with VCGE/VMVN
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
Dvicmp.ll6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
/external/llvm/test/CodeGen/ARM/
Dvfcmp.ll28 ; ole is implemented with VCGE
63 ; ugt is implemented with VCGE/VMVN
75 ; ult is implemented with VCGE/VMVN
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
Dvicmp.ll6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvfcmp.ll28 ; ole is implemented with VCGE
63 ; ugt is implemented with VCGE/VMVN
75 ; ult is implemented with VCGE/VMVN
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
Dvicmp.ll6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
/external/vixl/test/aarch32/config/
Dcond-dt-drt-drd-drn-drm-float.json37 "Vcge", // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2
38 // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h99 VCGE, // Vector compare greater than or equal. enumerator
DARMISelLowering.cpp869 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName()
3457 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
3461 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
3478 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); in LowerVSETCC()
3490 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
3528 if (Opc == ARMISD::VCGE) in LowerVSETCC()
3540 case ARMISD::VCGE: in LowerVSETCC()
DARMInstrNEON.td52 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
3673 // VCGE : Vector Compare Greater Than or Equal
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt1373 VCGE/VCGEQ output:
1374 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, }
1375 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1376 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, }
1377 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, }
1378 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1379 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, }
1380 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, }
1381 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, }
1382 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, }
[all …]
Dref-rvct-neon.txt1465 VCGE/VCGEQ output:
1466 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, }
1467 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1468 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, }
1469 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, }
1470 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1471 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, }
1472 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, }
1473 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, }
1474 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, }
[all …]
Dref-rvct-all.txt1465 VCGE/VCGEQ output:
1466 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, }
1467 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1468 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, }
1469 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, }
1470 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1471 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, }
1472 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, }
1473 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, }
1474 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, }
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.h98 VCGE, // Vector compare greater than or equal. enumerator
DARMScheduleSwift.td555 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
DARMISelLowering.cpp1173 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName()
4904 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4908 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
4925 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4937 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4975 if (Opc == ARMISD::VCGE) in LowerVSETCC()
4987 case ARMISD::VCGE: in LowerVSETCC()
DARMScheduleA9.td2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h126 VCGE, // Vector compare greater than or equal. enumerator
DARMScheduleSwift.td572 "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
DARMScheduleR52.td795 (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
DARMISelLowering.cpp1302 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName()
5678 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
5682 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
5701 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
5713 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
5750 if (Opc == ARMISD::VCGE) in LowerVSETCC()
5762 case ARMISD::VCGE: in LowerVSETCC()
DARMScheduleA57.td1009 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;
DARMScheduleA9.td2435 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
/external/v8/src/arm/
Dassembler-arm.cc4354 VCGE, enumerator
4390 case VCGE: in EncodeNeonBinOp()
4752 emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2)); in vcge()
/external/clang/include/clang/Basic/
Darm_neon.td552 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;

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