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Searched refs:VMOVDRR (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/ARM/
Dsplit-superreg-piece.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
Dsplit-superreg.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
Dsplit-superreg-complex.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h80 VMOVDRR, // Two gprs to double. enumerator
DARMISelLowering.cpp850 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; in getTargetNodeName()
1132 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2394 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
3092 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
3163 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
3228 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
6912 if (InDouble.getOpcode() == ARMISD::VMOVDRR) in PerformVMOVRRDCombine()
6977 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
7937 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); in PerformDAGCombine()
DARMInstrVFP.td27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
555 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
DARMFastISel.cpp1691 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1008 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1085 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1115 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1118 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1121 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1124 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2292 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
DARMISelLowering.h77 VMOVDRR, // Two gprs to double. enumerator
DARM.td125 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
DARMISelLowering.cpp1152 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; in getTargetNodeName()
1486 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1503 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
3108 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
3716 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
4250 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
4321 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
4479 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
9618 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP()) in PerformVMOVRRDCombine()
10328 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
[all …]
DARMScheduleSwift.td629 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
DARMFastISel.cpp2039 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
DARMInstrNEON.td5998 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5999 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
6001 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
6702 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6704 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td25 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1052 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1134 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1165 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1168 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1171 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1174 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2466 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
DARMISelLowering.h104 VMOVDRR, // Two gprs to double. enumerator
DARMInstructionSelector.cpp191 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
DARMISelLowering.cpp1278 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; in getTargetNodeName()
1685 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1702 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
3540 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
4243 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
4923 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
4994 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
5222 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
5979 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
11249 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP()) in PerformVMOVRRDCombine()
[all …]
DARM.td171 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
DARMScheduleSwift.td642 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
DARMScheduleA57.td809 def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;
DARMInstrNEON.td6273 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
6274 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
6276 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
7034 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
7036 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
7039 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
DARMFastISel.cpp2066 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-instruction-select.mir1827 ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc5330 { 1, 1, 2, 793, 796 }, // 579 VMOVDRR
6335 { 1, 70, 75, 2824, 2827 }, // 579 VMOVDRR
7340 { 1, 284, 286, 5748, 5751 }, // 579 VMOVDRR
11120 {DBGFIELD("VMOVDRR") 1, false, false, 17, 2, 1, 1, 0, 0}, // #579
12527 {DBGFIELD("VMOVDRR") 2, false, false, 1, 2, 33, 1, 0, 0}, // #579
13934 {DBGFIELD("VMOVDRR") 1, false, false, 18, 1, 9, 1, 0, 0}, // #579
15341 {DBGFIELD("VMOVDRR") 1, false, false, 18, 1, 9, 1, 0, 0}, // #579

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