| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | peephole-phi.mir | 23 # CHECK: %6:spr = VMOVSR %5, 14, $noreg
42 %6:spr = VMOVSR %5, 14, $noreg
66 %5:spr = VMOVSR %4, 14, $noreg
85 # CHECK: %5:spr = VMOVSR %4, 14, $noreg
102 %5:spr = VMOVSR %4, 14, $noreg
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| D | fcmp-xo.ll | 1 …m-arm-none-eabi -mattr=+execute-only,+fp-armv8 %s -o - | FileCheck --check-prefixes=CHECK,VMOVSR %s
35 ; VMOVSR: vmov [[FPREG:s[0-9]+]], [[REG]]
36 ; VMOVSR: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | subreg-remat.ll | 7 ; %vreg6:ssub_1<def> = VMOVSR %vreg0<kill>, pred:14, pred:%noreg, %vreg6<imp-def>; DPR_VFP2:%vreg…
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| /external/llvm/lib/Target/ARM/ |
| D | ARM.td | 125 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
128 "true", "Prefer VMOVSR">;
161 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
164 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
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| D | ARMBaseInstrInfo.cpp | 742 Opc = ARM::VMOVSR; in copyPhysReg()
4196 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4332 case ARM::VMOVSR: { in setExecutionDomain()
4501 case ARM::VMOVSR: in getPartialRegUpdateClearance()
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| D | ARMInstrVFP.td | 1009 def VMOVSR : AVConv4I<0b11100000, 0b1010,
2283 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2285 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2287 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
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| D | ARMFastISel.cpp | 410 TII.get(ARM::VMOVSR), MoveReg) in ARMMoveToFPReg()
1014 TII.get(ARM::VMOVSR), MoveReg) in ARMEmitLoad()
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| D | ARMScheduleSwift.td | 626 (instregex "VMOVSR$", "VSETLN")>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARM.td | 171 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
174 "true", "Prefer VMOVSR">;
218 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
222 "Convert VMOVSR, VMOVRS, "
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| D | ARMISelLowering.h | 105 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr enumerator
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| D | ARMInstrVFP.td | 27 def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>;
1053 def VMOVSR : AVConv4I<0b11100000, 0b1010,
1076 def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>;
2457 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2459 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2461 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
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| D | ARMBaseInstrInfo.cpp | 829 Opc = ARM::VMOVSR; in copyPhysReg()
4591 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4730 case ARM::VMOVSR: { in setExecutionDomain()
4896 case ARM::VMOVSR: in getPartialRegUpdateClearance()
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| D | ARMFastISel.cpp | 406 TII.get(ARM::VMOVSR), MoveReg) in ARMMoveToFPReg()
1014 TII.get(ARM::VMOVSR), MoveReg) in ARMEmitLoad()
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| D | ARMScheduleSwift.td | 639 (instregex "VMOVSR$", "VSETLN")>;
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| D | ARMISelLowering.cpp | 1281 case ARMISD::VMOVSR: return "ARMISD::VMOVSR"; in getTargetNodeName()
5982 return DAG.getNode(ARMISD::VMOVSR, DL, VT, in LowerConstantFP()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 490 TII.get(ARM::VMOVSR), MoveReg) in ARMMoveToIntReg()
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| D | ARMInstrVFP.td | 485 def VMOVSR : AVConv4I<0b11100000, 0b1010,
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| D | ARMBaseInstrInfo.cpp | 648 Opc = ARM::VMOVSR; in copyPhysReg()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 262 { "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", { ARM::FeatureNEONForFPMovs }, { } },
271 { "prefer-vmovsr", "Prefer VMOVSR", { ARM::FeaturePreferVMOVSR }, { } },
5327 { 1, 1, 2, 788, 790 }, // 576 VMOVSR
6332 { 1, 70, 75, 2816, 2818 }, // 576 VMOVSR
7337 { 1, 284, 286, 5740, 5742 }, // 576 VMOVSR
11117 {DBGFIELD("VMOVSR") 1, false, false, 17, 2, 1, 1, 0, 0}, // #576
12524 {DBGFIELD("VMOVSR") 1, false, false, 2, 1, 16, 1, 0, 0}, // #576
13931 {DBGFIELD("VMOVSR") 1, false, false, 18, 1, 9, 1, 0, 0}, // #576
15338 {DBGFIELD("VMOVSR") 2, false, false, 198, 3, 26, 1, 0, 0}, // #576
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| D | ARMGenFastISel.inc | 814 // FastEmit functions for ARMISD::VMOVSR.
820 return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
1144 return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
2586 case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill);
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| D | ARMGenAsmWriter.inc | 2338 540137U, // VMOVSR
5558 1024U, // VMOVSR
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| D | ARMGenMCCodeEmitter.inc | 1831 UINT64_C(234883600), // VMOVSR
9071 case ARM::VMOVSR: {
13104 Feature_HasVFP2 | 0, // VMOVSR = 1818
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| D | ARMGenAsmMatcher.inc | 10323 …{ 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondC…
10358 …{ 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondC…
10362 …{ 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondC…
10368 …{ 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondC…
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| D | ARMGenInstrInfo.inc | 1833 VMOVSR = 1818,
3822 VMOVSR = 576,
6513 …::Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #1818 = VMOVSR
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 1378 19186U, // VMOVSR
4171 1024U, // VMOVSR
|