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Searched refs:VMUL (Results 1 – 25 of 27) sorted by relevance

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/external/libhevc/common/arm/
Dihevc_resi_trans.s283 VMUL.S16 d12,d12,d4[0] @ d12 = 74*C3
312 VMUL.S32 q12,q1,d5[0] @ q12 = 29*S1 + 29*S4
313 VMUL.S32 q14,q1,d7[0] @ q14 = 84*S1 + 84*S4
314 VMUL.S32 q13,q13,d4[0] @ q13 = 74*S1 + 74*S2 - 74*S4
318 VMUL.S32 q9,q9,d4[0] @ q9 = 74*S3
690 VMUL.S32 q12,q2,d0[1] @ q12 = 83*(B0 - B3 - B4 + B7)
691 VMUL.S32 q2,q2,d0[0] @ q2 = 36*(B0 - B3 - B4 + B7)
692 VMUL.S32 q5,q9,d3[1] @ q5 = 89*(B0 - B7)
694 VMUL.S32 q4,q9,d3[0] @ q4 = 75*(B0 - B7)
708 VMUL.S32 q3,q9,d2[1] @ q3 = 50*(B0 - B7)
[all …]
Dihevc_resi_trans_32x32_a9q.s904 VMUL.S32 Q0,Q5,Q7 @4G0 4G1 4G2 4G3 * R1eeo[0] R1eeo[1] R1eeo[2] R1eeo[3]
909 …VMUL.S32 Q4,Q6,Q10 @g_ai4_ihevc_trans_32 * eeee[0] eeee[1] eeeo[0] eeeo[1] R1 -- dual iss…
912 VMUL.S32 Q9,Q5,Q7 @g_ai4_ihevc_trans_32[6][0-4] * eeo[0-4]
921 VMUL.S32 Q10,Q5,Q7 @g_ai4_ihevc_trans_32[10][0-4] * eeo[0-4] -- dual issued
926 VMUL.S32 Q11,Q5,Q7 @g_ai4_ihevc_trans_32[14][0-4] * eeo[0-4] -- dual issue
936 VMUL.S32 Q8,Q6,Q2 @g_ai4_ihevc_trans_16[2][0-3]*eo[0][0-3] R1
954 VMUL.S32 Q7,Q4,Q2 @eo[0][0-3]
962 VMUL.S32 Q8,Q9,Q2 @eo[0][0-3]
976 VMUL.S32 Q9,Q7,Q2 @eo[0][0-3] -- dual issue
985 VMUL.S32 Q4,Q0,Q2 @g_ai4_ihevc_trans_16[18][0-3]*eo[0][0-3] R1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleA57.td771 // VMUL takes 5 cyc for common case and 1 cyc for VMUL->VFMA chain (4 read adv.)
773 // from VFMA or from VMUL, so there will be 5 read advance.
774 // Zero latency (instead of one) for VMUL->VFMA shouldn't break something.
775 // The same situation with ASIMD VMUL/VFMA instructions
1026 "VMUL(v8i8|v4i16|v2i32|pd)", "VMULsl(v4i16|v2i32)",
1034 "VMUL(v16i8|v8i16|v4i32|pq)", "VMULsl(v8i16|v4i32)",
1182 def : InstRW<[A57WriteVMUL_VecFP], (instregex "VMUL(sl)?(fd|fq|hd|hq)")>;
DARMScheduleA8.td793 // Double-register FP VMUL
804 // Quad-register FP VMUL
DARMScheduleSwift.td615 (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
DARMScheduleA9.td1678 // Double-register FP VMUL
1700 // Quad-register FP VMUL
DARMInstrNEON.td4263 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4264 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dneon-spfp.ll19 ; This test makes sure we're not lowering VMUL.f32 D* (aka. NEON) for single-prec. FP ops, since
Dfp16-instructions.ll553 ; 23. VMUL
/external/llvm/test/CodeGen/ARM/
Dneon-spfp.ll19 ; This test makes sure we're not lowering VMUL.f32 D* (aka. NEON) for single-prec. FP ops, since
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt4597 VMUL output:
4598 VMUL:0:result_int8x8 [] = { fffffff0, 1, 12, 23, 34, 45, 56, 67, }
4599 VMUL:1:result_int16x4 [] = { fffffde0, fffffe02, fffffe24, fffffe46, }
4600 VMUL:2:result_int32x2 [] = { fffffcd0, fffffd03, }
4601 VMUL:3:result_int64x1 [] = { 3333333333333333, }
4602 VMUL:4:result_uint8x8 [] = { c0, 4, 48, 8c, d0, 14, 58, 9c, }
4603 VMUL:5:result_uint16x4 [] = { fab0, fb05, fb5a, fbaf, }
4604 VMUL:6:result_uint32x2 [] = { fffff9a0, fffffa06, }
4605 VMUL:7:result_uint64x1 [] = { 3333333333333333, }
4606 VMUL:8:result_poly8x8 [] = { c0, 84, 48, c, d0, 94, 58, 1c, }
[all …]
Dref-rvct-neon.txt5395 VMUL output:
5396 VMUL:0:result_int8x8 [] = { fffffff0, 1, 12, 23, 34, 45, 56, 67, }
5397 VMUL:1:result_int16x4 [] = { fffffde0, fffffe02, fffffe24, fffffe46, }
5398 VMUL:2:result_int32x2 [] = { fffffcd0, fffffd03, }
5399 VMUL:3:result_int64x1 [] = { 3333333333333333, }
5400 VMUL:4:result_uint8x8 [] = { c0, 4, 48, 8c, d0, 14, 58, 9c, }
5401 VMUL:5:result_uint16x4 [] = { fab0, fb05, fb5a, fbaf, }
5402 VMUL:6:result_uint32x2 [] = { fffff9a0, fffffa06, }
5403 VMUL:7:result_uint64x1 [] = { 3333333333333333, }
5404 VMUL:8:result_poly8x8 [] = { c0, 84, 48, c, d0, 94, 58, 1c, }
[all …]
Dref-rvct-all.txt5395 VMUL output:
5396 VMUL:0:result_int8x8 [] = { fffffff0, 1, 12, 23, 34, 45, 56, 67, }
5397 VMUL:1:result_int16x4 [] = { fffffde0, fffffe02, fffffe24, fffffe46, }
5398 VMUL:2:result_int32x2 [] = { fffffcd0, fffffd03, }
5399 VMUL:3:result_int64x1 [] = { 3333333333333333, }
5400 VMUL:4:result_uint8x8 [] = { c0, 4, 48, 8c, d0, 14, 58, 9c, }
5401 VMUL:5:result_uint16x4 [] = { fab0, fb05, fb5a, fbaf, }
5402 VMUL:6:result_uint32x2 [] = { fffff9a0, fffffa06, }
5403 VMUL:7:result_uint64x1 [] = { 3333333333333333, }
5404 VMUL:8:result_poly8x8 [] = { c0, 84, 48, c, d0, 94, 58, 1c, }
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMScheduleA8.td778 // Double-register FP VMUL
789 // Quad-register FP VMUL
DARMScheduleA9.td1649 // Double-register FP VMUL
1671 // Quad-register FP VMUL
DARMInstrNEON.td3410 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3411 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td793 // Double-register FP VMUL
804 // Quad-register FP VMUL
DARMScheduleSwift.td598 (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
DARMScheduleA9.td1678 // Double-register FP VMUL
1700 // Quad-register FP VMUL
DARMInstrNEON.td4172 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4173 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
/external/v8/src/arm/
Dassembler-arm.cc4349 VMUL, enumerator
4375 case VMUL: in EncodeNeonBinOp()
4480 emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2)); in vmul()
/external/clang/include/clang/Basic/
Darm_neon.td519 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSSE.td2753 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2755 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td3827 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3948 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, 1>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrAVX512.td5259 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnds,
5412 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512,

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