| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_dec_DCT2_64_asm.s | 51 VREV64.32 Q1, Q1
88 VREV64.32 Q2, Q2
91 VREV64.32 Q3, Q3
99 VREV64.16 D10, D10
120 VREV64.32 Q2, Q2
125 VREV64.32 Q3, Q3
136 VREV64.32 Q7, Q7
137 VREV64.32 Q6, Q6
140 VREV64.16 D10, D10
164 VREV64.32 Q2, Q2
[all …]
|
| D | ixheaacd_overlap_add2.s | 56 VREV64.16 D4, D6
57 VREV64.16 D5, D7
71 VREV64.16 Q6, Q7
85 VREV64.16 D4, D6
87 VREV64.16 D5, D7
106 VREV64.16 Q6, Q7
160 VREV64.32 D0, D6
161 VREV64.32 D1, D7
166 VREV64.16 D2, D2
167 VREV64.16 D3, D3
[all …]
|
| D | ixheaacd_dct3_32.s | 57 VREV64.32 Q1, Q1
74 VREV64.32 Q4, Q4
89 VREV64.32 Q1, Q1
119 VREV64.32 Q4, Q4
136 VREV64.32 Q1, Q1
152 VREV64.32 Q4, Q4
291 VREV64.32 Q2, Q2
294 VREV64.32 Q3, Q3
307 VREV64.16 D8, D8
343 VREV64.32 Q13, Q13
[all …]
|
| D | ixheaacd_pre_twiddle_compute.s | 111 VREV64.16 Q5, Q4
116 VREV64.16 Q0, Q0
117 VREV64.16 Q2, Q2
168 VREV64.16 Q5, Q4
178 VREV64.16 Q0, Q0
181 VREV64.16 Q2, Q2
237 VREV64.16 Q5, Q4
244 VREV64.16 Q0, Q0
247 VREV64.16 Q2, Q2
326 VREV64.16 Q0, Q0
[all …]
|
| D | ixheaacd_no_lap1.s | 48 VREV64.32 Q13, Q13
67 VREV64.32 Q10, Q10
79 VREV64.32 Q13, Q13
99 VREV64.32 Q10, Q10
|
| D | ixheaacd_post_twiddle.s | 110 VREV64.16 Q6, Q4
168 VREV64.16 Q6, Q4
191 VREV64.32 Q7, Q7
204 VREV64.32 Q12, Q12
276 VREV64.16 Q6, Q4
299 VREV64.32 Q7, Q7
310 VREV64.32 Q12, Q12
399 VREV64.32 Q7, Q7
410 VREV64.32 Q12, Q12
435 VREV64.16 Q6, Q4
[all …]
|
| D | ixheaacd_overlap_add1.s | 49 VREV64.32 Q3, Q3
60 VREV64.16 Q1, Q1
106 VREV64.32 Q3, Q3
115 VREV64.16 Q1, Q1
149 VREV64.32 Q3, Q3
168 VREV64.16 Q1, Q1
212 VREV64.32 Q3, Q3
220 VREV64.16 Q1, Q1
|
| D | ixheaacd_mps_synt_post_fft_twiddle.s | 56 VREV64.32 D1, D1
57 VREV64.32 D0, D0
|
| D | ixheaacd_post_twiddle_overlap.s | 195 VREV64.16 Q0, Q0
196 VREV64.16 Q1, Q1
220 VREV64.16 Q5, Q5
223 VREV64.16 Q6, Q6
391 VREV64.16 Q0, Q0
394 VREV64.16 Q1, Q1
408 VREV64.16 Q5, Q5
411 VREV64.16 Q6, Q6
654 VREV64.16 Q0, Q0
657 VREV64.16 Q1, Q1
[all …]
|
| D | ixheaacd_calc_pre_twid.s | 44 VREV64.32 D8, D8
45 VREV64.32 D9, D10
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 199 VREV64.S16 Q10,Q10 @ Rev 17-24 row 1 -- dual issue
201 VREV64.S16 Q11,Q11 @ Rev 25-32 row 1 -- dual issue
207 VREV64.S16 Q2,Q2 @ Rev 17-24 row 2
209 VREV64.S16 Q3,Q3 @ Rev 25-32 row 2
216 VREV64.16 Q5, Q5 @ Rev 9-16 of e[k], row 1
221 VREV64.16 Q9, Q9 @ Rev 9-16 of e[k], row 2
228 VREV64.S16 D8,D1 @ rev ee[k] k-> 4-7 row 1
232 VREV64.S16 D9,D5 @ rev ee[k] k-> 4-7 row 2
835 VREV64.32 Q15,Q15 @ Q15: [16 1] [16 0] [24 1] [24 0]
852 VREV64.S32 Q4,Q4 @Rev 17-20 R1
[all …]
|
| D | ihevc_resi_trans.s | 1023 VREV64.S16 Q5,Q5 @Rev row 1
1024 VREV64.S16 Q7,Q7 @Rev row 2
1033 VREV64.S16 D24,D17 @rev e[k] k-> 4-7 row 1
1034 VREV64.S16 D25,D21 @rev e[k] k-> 4-7 row 2
1347 VREV64.32 Q15,Q15
1368 VREV64.S32 Q2,Q2 @Rev 9-12 R1
1369 VREV64.S32 Q3,Q3 @Rev 12-16 R1
1370 VREV64.S32 Q6,Q6 @Rev 9-12 R2
1371 VREV64.S32 Q7,Q7 @Rev 12-16 R2
1383 VREV64.S32 Q9 ,Q9 @rev e[k] k-> 4-7 R1, dual issued with prev. instruction
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 155 VREV64, // reverse elements within 64-bit doublewords enumerator
|
| D | ARMISelLowering.cpp | 905 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4270 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
4367 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vrev.ll | 151 ; vrev <4 x i16> should use VREV32 and not VREV64
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 2999 VREV64 output:
3000 VREV64:44:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3001 VREV64:45:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3002 VREV64:46:result_int32x2 [] = { fffffff1, fffffff0, }
3003 VREV64:47:result_int64x1 [] = { 3333333333333333, }
3004 VREV64:48:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3005 VREV64:49:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3006 VREV64:50:result_uint32x2 [] = { fffffff1, fffffff0, }
3007 VREV64:51:result_uint64x1 [] = { 3333333333333333, }
3008 VREV64:52:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
|
| D | ref-rvct-neon.txt | 3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
|
| D | ref-rvct-all.txt | 3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 153 VREV64, // reverse elements within 64-bit doublewords enumerator
|
| D | ARMScheduleSwift.td | 549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1208 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4489 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6143 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
6206 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6269 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 185 VREV64, // reverse elements within 64-bit doublewords enumerator
|
| D | ARMScheduleSwift.td | 566 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1337 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
5232 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
5651 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
6968 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
7031 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
7094 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4787 enum NeonSizedOp { VZIP, VUZP, VREV16, VREV32, VREV64, VTRN }; enumerator
4805 case VREV64: in EncodeNeonSizedOp()
4879 emit(EncodeNeonSizedOp(VREV64, NEON_Q, size, dst.code(), src.code())); in vrev64()
|