| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans.s | 324 VRSHRN.S32 d26,q13,#8
331 VRSHRN.S32 d24,q12,#8
332 VRSHRN.S32 d28,q14,#8
333 VRSHRN.S32 d30,q15,#8 @ Truncating the last 8 bits
700 VRSHRN.I32 d28,q14,#5 @ Truncating last 11 bits in G0
702 VRSHRN.I32 d30,q15,#5 @ Truncating last 11 bits in G4
709 VRSHRN.I32 d24,q12,#11 @ Truncating last 11 bits in G2
711 VRSHRN.I32 d4,q2,#11 @ Truncating last 11 bits in G6
737 VRSHRN.I32 d10,q5,#11 @ Truncating last 11 bits in G1
738 VRSHRN.I32 d8,q4,#11 @ Truncating last 11 bits in G3
[all …]
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| D | ihevc_resi_trans_32x32_a9q.s | 915 VRSHRN.S32 D8,Q4,#SHIFT_32 @ROUND NARROW R1 -- dual issued in 2nd cycle
956 VRSHRN.S32 D0,Q0,#SHIFT_32 @ Shift by SHIFT and Round the result
1001 VRSHRN.S32 D14,Q8,#SHIFT_32
1039 VRSHRN.S32 D16,Q8,#SHIFT_32 @ dual issue
1089 VRSHRN.S32 D16,Q8,#SHIFT_32 @ duall issue
1134 VRSHRN.S32 D16,Q8,#SHIFT_32 @ dual issue
1177 VRSHRN.S32 D16,Q8,#SHIFT_32
1215 VRSHRN.S32 D16,Q8,#SHIFT_32
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 121 VRSHRN, // ...right narrow enumerator
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| D | ARMInstrNEON.td | 82 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
4160 // VRSHRN : Vector Rounding Shift Right and Narrow
4161 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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| D | ARMISelLowering.cpp | 888 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; in getTargetNodeName()
7646 VShiftOpc = ARMISD::VRSHRN; break; in PerformIntrinsicCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 116 VRSHRN, // ...right narrow enumerator
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| D | ARMScheduleSwift.td | 565 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
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| D | ARMInstrNEON.td | 524 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
5490 // VRSHRN : Vector Rounding Shift Right and Narrow
5491 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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| D | ARMISelLowering.cpp | 1188 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; in getTargetNodeName()
10638 VShiftOpc = ARMISD::VRSHRN; break; in PerformIntrinsicCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 144 VRSHRN, // ...right narrow enumerator
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| D | ARMScheduleSwift.td | 582 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
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| D | ARMScheduleR52.td | 830 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VRSHL", "VRSHR", "VRSHRN", "VT…
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| D | ARMScheduleA57.td | 1121 "VRSHRN")>;
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| D | ARMInstrNEON.td | 514 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
5766 // VRSHRN : Vector Rounding Shift Right and Narrow
5767 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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| D | ARMISelLowering.cpp | 1317 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; in getTargetNodeName()
12295 VShiftOpc = ARMISD::VRSHRN; break; in PerformIntrinsicCombine()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 6377 // FastEmit functions for ARMISD::VRSHRN.
6405 …case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill…
6518 // FastEmit functions for ARMISD::VRSHRN.
6546 …case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKil…
6659 // FastEmit functions for ARMISD::VRSHRN.
6687 …case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKil…
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| D | ARMGenDAGISel.inc | 36057 /* 79432*/ /*SwitchOpcode*/ 102, TARGET_VAL(ARMISD::VRSHRN),// ->79537
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