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Searched refs:Vt (Results 1 – 25 of 194) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPatternsHVX.td24 def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
25 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;
196 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
197 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
198 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
199 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
200 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
201 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
291 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
292 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
[all …]
DHexagonISelLoweringHVX.cpp1205 SDValue Vt = Op.getOperand(1); in LowerHvxMul() local
1215 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMul()
1230 return getInstr(Hexagon::V6_vmpyih, dl, ResTy, {Vs, Vt}, DAG); in LowerHvxMul()
1237 SDValue T0 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG); in LowerHvxMul()
1240 {T1, Vs, Vt}, DAG); in LowerHvxMul()
1259 SDValue Vt = Op.getOperand(1); in LowerHvxMulh() local
1273 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
1303 SDValue T0 = getInstr(Hexagon::V6_vmpyewuh, dl, ResTy, {Vt, Vs}, DAG); in LowerHvxMulh()
1307 {T0, S0, Vt}, DAG); in LowerHvxMulh()
1311 SDValue T2 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {S0, Vt}, DAG); in LowerHvxMulh()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td582 def : InstAlias<"$Vt=vmem($Rs)",
583 (V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
586 def : InstAlias<"$Vt=vmem($Rs):nt",
587 (V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
590 def : InstAlias<"vmem($Rs)=$Vt",
591 (V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
594 def : InstAlias<"vmem($Rs):nt=$Vt",
595 (V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
598 def : InstAlias<"vmem($Rs)=$Vt.new",
599 (V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
[all …]
/external/capstone/arch/AArch64/
DAArch64GenAsmWriter.inc8029 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR)
8041 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR)
8053 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR)
8065 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR)
8077 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR)
8089 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR)
8101 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR)
8113 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR)
8125 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR)
8137 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR)
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td8220 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
8221 bits<5> Vt;
8231 let Inst{4-0} = Vt;
8236 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
8237 bits<5> Vt;
8249 let Inst{4-0} = Vt;
8257 // "ld1\t$Vt, [$Rn], #16"
8259 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
8260 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8263 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td8698 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
8699 bits<5> Vt;
8709 let Inst{4-0} = Vt;
8714 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
8715 bits<5> Vt;
8727 let Inst{4-0} = Vt;
8735 // "ld1\t$Vt, [$Rn], #16"
8737 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
8738 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8741 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmWriter.inc15405 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR)
15418 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR)
15431 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR)
15444 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR)
15457 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR)
15470 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR)
15483 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR)
15496 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR)
15557 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR)
15570 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR)
[all …]
DAArch64GenAsmWriter1.inc16093 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR)
16106 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR)
16119 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR)
16132 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR)
16145 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR)
16158 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR)
16171 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR)
16184 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR)
16245 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR)
16258 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR)
[all …]
DAArch64GenDAGISel.inc63 /* 14*/ OPC_RecordChild0, // #1 = $Vt
82 …// Src: (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[iPTR] }), (ro_Wind…
83 …// Dst: (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), G…
92 …// Src: (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[iPTR] }), (ro_Xind…
93 …// Dst: (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), G…
102 …// Src: (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[iPTR] }), (am_inde…
103 …// Dst: (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GP…
112 …// Src: (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[iPTR] }), (am_unsc…
113 …// Dst: (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GP…
133 …// Src: (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Pred…
[all …]
/external/honggfuzz/examples/apache-httpd/corpus_http1/
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/external/honggfuzz/examples/apache-httpd/corpus_http2/
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/external/cldr/tools/cldr-unittest/src/org/unicode/cldr/unittest/data/transformtest/
Dund-fonipa-t-und-fonxsamp.txt82 str\Vt stɹʌt
Dund-fonxsamp-t-und-fonipa.txt83 stɹʌt str\Vt
/external/icu/icu4c/source/data/unit/
Duz.txt1548 dnam{"Vt"}
1549 one{"{0} Vt"}
1550 other{"{0} Vt"}
/external/ImageMagick/PerlMagick/t/reference/write/filter/
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/external/ImageMagick/PerlMagick/t/reference/read/
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/external/ImageMagick/PerlMagick/t/reference/filter/
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/external/ImageMagick/PerlMagick/t/reference/write/jng/
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