| /external/llvm/lib/Target/AMDGPU/ |
| D | SISchedule.td | 26 def WriteBarrier : SchedWrite;
98 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
|
| D | SIInstructions.td | 485 let SchedRW = [WriteBarrier];
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SISchedule.td | 26 def WriteBarrier : SchedWrite;
107 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
|
| D | SOPInstructions.td | 915 let SchedRW = [WriteBarrier];
|
| /external/gemmlowp/internal/ |
| D | multi_thread_gemm.h | 58 inline void WriteBarrier() { in WriteBarrier() function
181 WriteBarrier(); in DecrementCount()
327 WriteBarrier(); in StartWork()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkor.td | 99 def : WriteRes<WriteBarrier, []> { let Unsupported = 1; }
|
| D | AArch64Schedule.td | 80 def WriteBarrier : SchedWrite; // Memory barrier.
|
| D | AArch64SchedKryo.td | 103 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedThunderX.td | 148 def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
|
| D | AArch64SchedA53.td | 120 def : WriteRes<WriteBarrier, [A53UnitB]>;
|
| D | AArch64SchedCyclone.td | 295 def : WriteRes<WriteBarrier, [CyUnitLS]>;
|
| D | AArch64SchedExynosM1.td | 223 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedExynosM3.td | 266 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedA57.td | 105 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedThunderX2T99.td | 390 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64InstrFormats.td | 1093 Sched<[WriteBarrier]> {
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 80 def WriteBarrier : SchedWrite; // Memory barrier.
|
| D | AArch64SchedKryo.td | 98 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedA53.td | 118 def : WriteRes<WriteBarrier, [A53UnitB]>;
|
| D | AArch64SchedM1.td | 145 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedCyclone.td | 293 def : WriteRes<WriteBarrier, [CyUnitLS]>;
|
| D | AArch64SchedVulcan.td | 220 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64SchedA57.td | 103 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
| D | AArch64InstrFormats.td | 882 Sched<[WriteBarrier]> {
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSubtargetInfo.inc | 1529 {DBGFIELD("WriteBarrier") 1, false, false, 3, 1, 4, 1, 0, 0}, // #13
2515 {DBGFIELD("WriteBarrier") 1, false, false, 0, 0, 4, 1, 0, 0}, // #13
3501 {DBGFIELD("WriteBarrier") 1, false, false, 165, 1, 4, 1, 0, 0}, // #13
4487 {DBGFIELD("WriteBarrier") 1, false, false, 0, 0, 4, 1, 0, 0}, // #13
5473 {DBGFIELD("WriteBarrier") 1, false, false, 0, 0, 4, 1, 0, 0}, // #13
6459 {DBGFIELD("WriteBarrier") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #13
7445 {DBGFIELD("WriteBarrier") 1, false, false, 0, 0, 4, 1, 0, 0}, // #13
8431 {DBGFIELD("WriteBarrier") 1, false, false, 3, 1, 4, 1, 0, 0}, // #13
9417 {DBGFIELD("WriteBarrier") 1, false, false, 0, 0, 4, 1, 0, 0}, // #13
|