| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 175 .addReg(TIP.first) in runOnMachineFunction()
178 .addReg(0)); in runOnMachineFunction()
982 .addReg(0)); in EmitJumpTableInsts()
1242 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1246 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1258 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1262 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1269 .addReg(ARM::LR) in EmitInstruction()
1270 .addReg(ARM::PC) in EmitInstruction()
1273 .addReg(0) in EmitInstruction()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 146 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
148 .addReg(Scratch) in expandAtomicCmpSwapSubword()
149 .addReg(Mask); in expandAtomicCmpSwapSubword()
151 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
159 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
160 .addReg(Mask2); in expandAtomicCmpSwapSubword()
162 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
163 .addReg(ShiftNewVal); in expandAtomicCmpSwapSubword()
165 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
166 .addReg(Ptr) in expandAtomicCmpSwapSubword()
[all …]
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| D | MipsFastISel.cpp | 219 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
224 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
331 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
368 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
371 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
380 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
395 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
403 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
421 .addReg(MFI->getGlobalBaseReg()) in materializeGV()
427 .addReg(DestReg) in materializeGV()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 154 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
155 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
156 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
159 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
160 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
161 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
187 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
188 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
189 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
195 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 162 .addReg(ThumbIndirectPads[i].first) in runOnMachineFunction()
165 .addReg(0)); in runOnMachineFunction()
1075 .addReg(0)); in EmitJumpTableInsts()
1311 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1315 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1327 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1331 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1338 .addReg(ARM::LR) in EmitInstruction()
1339 .addReg(ARM::PC) in EmitInstruction()
1342 .addReg(0) in EmitInstruction()
[all …]
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| D | ARMFrameLowering.cpp | 257 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
262 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
271 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
275 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
283 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
465 .addImm((unsigned)ARMCC::AL).addReg(0) in emitPrologue()
467 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
477 .addImm((unsigned)ARMCC::AL).addReg(0) in emitPrologue()
478 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
479 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 137 .addReg(SrcReg) in HandleVRSaveUpdate()
141 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
146 .addReg(SrcReg) in HandleVRSaveUpdate()
150 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
155 .addReg(SrcReg) in HandleVRSaveUpdate()
159 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
163 .addReg(DstReg, RegState::Kill) in HandleVRSaveUpdate()
317 .addReg(PPC::X31) in emitPrologue()
319 .addReg(PPC::X1); in emitPrologue()
323 .addReg(PPC::X0) in emitPrologue()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrBuilder.h | 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
140 return MIB.addReg(0); in addFullAddress()
178 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
179 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0); in addConstantPoolReference()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 128 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
145 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
150 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
160 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
168 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
169 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
178 MIB.addReg(AM.Base.Reg); in addFullAddress()
184 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
190 return MIB.addReg(0); in addFullAddress()
227 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.cpp | 38 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
41 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
80 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
83 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
94 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
96 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
101 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
103 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
108 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
110 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
156 MIB.addReg(AM.Base.Reg); in addFullAddress()
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
168 return MIB.addReg(0); in addFullAddress()
205 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
206 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0); in addConstantPoolReference()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 171 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
175 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
326 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
335 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
358 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
376 .addReg(MFI->getGlobalBaseReg()) in materializeGV()
382 .addReg(DestReg) in materializeGV()
[all …]
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| D | MipsLongBranch.cpp | 235 MIB.addReg(MO.getReg()); in replaceBranch()
299 .addReg(Mips::SP).addImm(-8); in expandToLongBranch()
300 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
301 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
324 .addReg(Mips::AT) in expandToLongBranch()
331 .addReg(Mips::RA).addReg(Mips::AT); in expandToLongBranch()
333 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
338 .addReg(Mips::SP).addImm(8); in expandToLongBranch()
342 .addReg(Mips::ZERO).addReg(Mips::AT); in expandToLongBranch()
344 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT); in expandToLongBranch()
[all …]
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 511 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg)); in SpillReg()
516 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg)); in RestoreReg()
547 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg)); in InstrumentMemOperandPrologue()
601 .addReg(X86::ESP) in EmitCallAsanReport()
602 .addReg(X86::ESP) in EmitCallAsanReport()
605 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(32))); in EmitCallAsanReport()
628 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg( in InstrumentMemOperandSmall()
631 .addReg(ShadowRegI32) in InstrumentMemOperandSmall()
632 .addReg(ShadowRegI32) in InstrumentMemOperandSmall()
648 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8)); in InstrumentMemOperandSmall()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 524 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg)); in SpillReg()
529 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg)); in RestoreReg()
560 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg)); in InstrumentMemOperandPrologue()
614 .addReg(X86::ESP) in EmitCallAsanReport()
615 .addReg(X86::ESP) in EmitCallAsanReport()
618 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(32))); in EmitCallAsanReport()
641 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg( in InstrumentMemOperandSmall()
644 .addReg(ShadowRegI32) in InstrumentMemOperandSmall()
645 .addReg(ShadowRegI32) in InstrumentMemOperandSmall()
661 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8)); in InstrumentMemOperandSmall()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 370 .addReg(SrcReg) in HandleVRSaveUpdate()
374 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
379 .addReg(SrcReg) in HandleVRSaveUpdate()
383 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
388 .addReg(SrcReg) in HandleVRSaveUpdate()
392 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
396 .addReg(DstReg, RegState::Kill) in HandleVRSaveUpdate()
862 MIB.addReg(MustSaveCRs[i], CrState); in emitPrologue()
864 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
866 .addReg(SPReg); in emitPrologue()
[all …]
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| D | PPCAsmPrinter.cpp | 390 .addReg(ScratchReg) in LowerPATCHPOINT()
394 .addReg(ScratchReg) in LowerPATCHPOINT()
395 .addReg(ScratchReg) in LowerPATCHPOINT()
399 .addReg(ScratchReg) in LowerPATCHPOINT()
400 .addReg(ScratchReg) in LowerPATCHPOINT()
404 .addReg(ScratchReg) in LowerPATCHPOINT()
405 .addReg(ScratchReg) in LowerPATCHPOINT()
411 .addReg(PPC::X2) in LowerPATCHPOINT()
413 .addReg(PPC::X1)); in LowerPATCHPOINT()
423 .addReg(PPC::X2) in LowerPATCHPOINT()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUFrameLowering.cpp | 125 .addReg(SPU::R1); in emitPrologue()
129 .addReg(SPU::R1); in emitPrologue()
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) in emitPrologue()
138 .addReg(SPU::R1); in emitPrologue()
142 .addReg(SPU::R2) in emitPrologue()
143 .addReg(SPU::R1); in emitPrologue()
145 .addReg(SPU::R1) in emitPrologue()
146 .addReg(SPU::R2); in emitPrologue()
148 .addReg(SPU::R2) in emitPrologue()
151 .addReg(SPU::R2) in emitPrologue()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaFrameLowering.cpp | 57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist); in emitPrologue()
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist); in emitPrologue()
83 .addReg(Alpha::R30); in emitPrologue()
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
99 .addReg(Alpha::R30).addReg(Alpha::R30); in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
124 .addReg(Alpha::R15); in emitEpilogue()
127 .addImm(0).addReg(Alpha::R15); in emitEpilogue()
[all …]
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| D | AlphaLLRP.cpp | 78 .addReg(Alpha::R31) in runOnMachineFunction()
79 .addReg(Alpha::R31); in runOnMachineFunction()
90 .addReg(Alpha::R31) in runOnMachineFunction()
91 .addReg(Alpha::R31); in runOnMachineFunction()
93 .addReg(Alpha::R31) in runOnMachineFunction()
94 .addReg(Alpha::R31); in runOnMachineFunction()
104 .addReg(Alpha::R31).addReg(Alpha::R31); in runOnMachineFunction()
106 .addReg(Alpha::R31).addReg(Alpha::R31); in runOnMachineFunction()
108 .addReg(Alpha::R31).addReg(Alpha::R31); in runOnMachineFunction()
141 .addReg(Alpha::R31).addReg(Alpha::R31); in runOnMachineFunction()
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| D | AlphaInstrInfo.cpp | 103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
113 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
127 .addReg(SrcReg) in copyPhysReg()
128 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
131 .addReg(SrcReg) in copyPhysReg()
132 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
135 .addReg(SrcReg) in copyPhysReg()
136 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SIMDInstrOpt.cpp | 448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
452 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
453 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
454 .addReg(DupDest, Src2IsKill); in optimizeVectElement()
460 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
464 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
465 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
564 .addReg(StReg[0]) in optimizeLdStInterleave()
565 .addReg(StReg[1]); in optimizeLdStInterleave()
567 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 237 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
238 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
239 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
240 .addReg(AMDGPU::VGPR0, RegState::Undef); in skipIfDead()
255 .addReg(Vcc); in If()
258 .addReg(AMDGPU::EXEC) in If()
259 .addReg(Reg); in If()
266 .addReg(Reg); in If()
279 .addReg(Src); // Saved EXEC in Else()
286 .addReg(AMDGPU::EXEC) in Else()
[all …]
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