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Searched refs:addRegisterClass (Results 1 – 25 of 60) sorted by relevance

123

/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXISelLowering.cpp38 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass); in PTXTargetLowering()
39 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass); in PTXTargetLowering()
40 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass); in PTXTargetLowering()
41 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass); in PTXTargetLowering()
42 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass); in PTXTargetLowering()
43 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass); in PTXTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp26 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
27 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
28 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
29 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
30 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
31 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
40 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
41 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
42 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
43 addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
[all …]
DHexagonISelLowering.cpp1258 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1259 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1260 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering()
1261 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1262 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1263 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1264 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1265 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1266 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1267 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1736 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1737 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1738 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering()
1739 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1740 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1741 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1742 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1743 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1744 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1745 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp54 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
55 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
56 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
57 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
59 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
60 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); in SystemZTargetLowering()
50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); in SystemZTargetLowering()
51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); in SystemZTargetLowering()
52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); in SystemZTargetLowering()
55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); in SystemZTargetLowering()
56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); in SystemZTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DRegisterBankEmitter.cpp73 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() function in __anon6b49e9f90111::RegisterBank
296 Bank.addRegisterClass(RC); in run()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp53 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
54 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
55 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
56 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp58 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
59 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
61 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
62 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
64 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
65 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
66 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
68 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
69 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
71 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
[all …]
DR600ISelLowering.cpp36 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
39 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
40 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
41 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp107 addRegisterClass(MVT::i8, SPU::R8CRegisterClass); in SPUTargetLowering()
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass); in SPUTargetLowering()
109 addRegisterClass(MVT::i32, SPU::R32CRegisterClass); in SPUTargetLowering()
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass); in SPUTargetLowering()
111 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass); in SPUTargetLowering()
112 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass); in SPUTargetLowering()
113 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass); in SPUTargetLowering()
394 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass); in SPUTargetLowering()
395 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass); in SPUTargetLowering()
396 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass); in SPUTargetLowering()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2ISelLowering.cpp174 addRegisterClass(MVT::i32, &Nios2::CPURegsRegClass); in Nios2TargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp50 addRegisterClass(MVT::i32, BF::DRegisterClass); in BlackfinTargetLowering()
51 addRegisterClass(MVT::i16, BF::D16RegisterClass); in BlackfinTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
89 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); in MipsSETargetLowering()
127 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); in MipsSETargetLowering()
172 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
177 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
314 addRegisterClass(Ty, RC); in addMSAIntType()
367 addRegisterClass(Ty, RC); in addMSAFloatType()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp54 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); in AlphaTargetLowering()
55 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); in AlphaTargetLowering()
56 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); in AlphaTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp63 addRegisterClass(MVT::i64, &BPF::GPRRegClass); in BPFTargetLowering()
65 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp118 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
119 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
121 addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass); in SITargetLowering()
122 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
124 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
125 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
126 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
128 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
129 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
131 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
[all …]
DR600ISelLowering.cpp58 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
59 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); in MipsSETargetLowering()
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
247 addRegisterClass(Ty, RC); in addMSAIntType()
296 addRegisterClass(Ty, RC); in addMSAFloatType()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp83 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering()
85 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering()
86 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering()
88 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering()
89 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering()
91 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering()
92 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering()
95 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
97 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
100 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering()
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering()
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering()
96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering()
97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering()
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering()
100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering()
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
106 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp364 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
365 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
366 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
367 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
368 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
369 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
370 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass); in NVPTXTargetLowering()
371 addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass); in NVPTXTargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcISelLowering.cpp693 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); in SparcTargetLowering()
694 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); in SparcTargetLowering()
695 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); in SparcTargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp95 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); in MipsTargetLowering()
96 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); in MipsTargetLowering()
99 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); in MipsTargetLowering()
104 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); in MipsTargetLowering()
106 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); in MipsTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp49 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
52 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); in RISCVTargetLowering()
54 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); in RISCVTargetLowering()

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