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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td29 def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
67 defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
71 defm SMAX_ZI : sve_int_arith_imm1<0b00, "smax", simm8>;
154 defm FMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, "fmla">;
159 defm FMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b00, "fmad">;
215 defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo">;
230 def BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa">;
297 defm LD1RB_IMM : sve_mem_ld_dup<0b00, 0b00, "ld1rb", Z_b, ZPR8, uimm6s1>;
298 defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>;
299 defm LD1RB_S_IMM : sve_mem_ld_dup<0b00, 0b10, "ld1rb", Z_s, ZPR32, uimm6s1>;
[all …]
DSVEInstrFormats.td263 def _B : sve_int_ptrue<0b00, opc, asm, PPR8>;
351 def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>;
386 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>;
393 def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>;
400 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>;
455 def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>;
573 let AsmString = !if(!eq(opc{2,0}, 0b00),
628 def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>;
723 def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>;
753 def _B : sve_int_perm_reverse_z<0b00, asm, ZPR8>;
[all …]
DAArch64InstrFormats.td1183 let Inst{20-19} = 0b00;
1211 let Inst{20-19} = 0b00;
1634 let Inst{15-14} = 0b00;
1731 let Inst{15-14} = 0b00;
2594 let Inst{11-10} = 0b00;
2866 let Inst{25-24} = 0b00;
2881 let Inst{25-24} = 0b00;
2978 let Inst{25-24} = 0b00;
3056 let Inst{25-24} = 0b00;
3128 let Inst{25-24} = 0b00;
[all …]
DAArch64InstrInfo.td480 def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">;
482 def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">;
485 def EOR3 : CryptoRRRR_16B<0b00, "eor3">;
491 def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">;
496 def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">;
504 def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;
548 def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;
552 def IZA : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>;
561 def XPACI : SignAuthZero<0b100, 0b00, "xpaci">;
639 defm MOVN : MoveImmediate<0b00, "movn">;
[all …]
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrFormats.td68 let Inst{7-6} = 0b00;
84 let Inst{10-9} = 0b00;
117 let Inst{10-9} = 0b00;
172 let Inst{10-9} = 0b00;
219 let Inst{10-9} = 0b00;
DMipsMSAInstrInfo.td397 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
402 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
407 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
412 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
417 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
422 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
429 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
431 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
436 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
441 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td1111 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1118 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1143 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1150 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1175 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1183 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1207 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1216 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1240 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1248 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
[all …]
DARMInstrThumb2.td514 let Inst{7-6} = 0b00; // imm2
515 let Inst{5-4} = 0b00; // type
592 let Inst{7-6} = 0b00; // imm2
593 let Inst{5-4} = 0b00; // type
681 let Inst{7-6} = 0b00; // imm2
682 let Inst{5-4} = 0b00; // type
722 let Inst{7-6} = 0b00; // imm2
723 let Inst{5-4} = 0b00; // type
845 let Inst{7-6} = 0b00; // imm2
846 let Inst{5-4} = 0b00; // type
[all …]
/external/skia/src/core/
DSkMatrix44.cpp455 double b00 = a00 * a11 - a01 * a10; in determinant() local
469 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
570 double b00 = a00 * a11 - a01 * a10; in invert() local
581 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
591 b00 *= invdet; in invert()
611 inverse->fMat[2][2] = SkDoubleToMScalar(b00); in invert()
615 inverse->fMat[3][2] = SkDoubleToMScalar(a31 * b01 - a30 * b03 - a32 * b00); in invert()
628 double b00 = a00 * a11 - a01 * a10; in invert() local
642 double det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in invert()
652 b00 *= invdet; in invert()
[all …]
/external/skqp/src/core/
DSkMatrix44.cpp455 double b00 = a00 * a11 - a01 * a10; in determinant() local
469 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
570 double b00 = a00 * a11 - a01 * a10; in invert() local
581 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
591 b00 *= invdet; in invert()
611 inverse->fMat[2][2] = SkDoubleToMScalar(b00); in invert()
615 inverse->fMat[3][2] = SkDoubleToMScalar(a31 * b01 - a30 * b03 - a32 * b00); in invert()
628 double b00 = a00 * a11 - a01 * a10; in invert() local
642 double det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in invert()
652 b00 *= invdet; in invert()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td961 let Inst{20-19} = 0b00;
989 let Inst{20-19} = 0b00;
1373 let Inst{15-14} = 0b00;
2236 let Inst{11-10} = 0b00;
2474 let Inst{25-24} = 0b00;
2489 let Inst{25-24} = 0b00;
2586 let Inst{25-24} = 0b00;
2664 let Inst{25-24} = 0b00;
2736 let Inst{25-24} = 0b00;
2808 let Inst{25-24} = 0b00;
[all …]
DAArch64InstrInfo.td443 defm MOVN : MoveImmediate<0b00, "movn">;
703 defm LSLV : Shift<0b00, "lsl", shl>;
801 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
806 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
886 defm AND : LogicalImm<0b00, "and", and, "bic">;
903 defm AND : LogicalReg<0b00, 0, "and", and>;
904 defm BIC : LogicalReg<0b00, 1, "bic",
1005 defm SBFM : BitfieldImm<0b00, "sbfm">;
1112 defm CSEL : CondSelect<0, 0b00, "csel">;
1116 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
[all …]
/external/protobuf/src/google/protobuf/stubs/
Dint128.h343 uint64 b00 = b.lo_ & 0xffffffffu; variable
347 uint64 c96 = a96 * b00 + a64 * b32 + a32 * b64 + a00 * b96;
348 uint64 c64 = a64 * b00 + a32 * b32 + a00 * b64;
352 *this += uint128(a32 * b00) << 32;
354 *this += a00 * b00;
/external/eigen/Eigen/src/SparseLU/
DSparseLU_gemm_kernel.h74 Packet b00, b10, b20, b30, b01, b11, b21, b31; in sparselu_gemm() local
75 { b00 = pset1<Packet>(Bc0[0]); } in sparselu_gemm()
111 KMADD(c0, a0, b00, t0) \ in sparselu_gemm()
178 Packet b00, b10, b20, b30; in sparselu_gemm() local
179 b00 = pset1<Packet>(Bc0[0]); in sparselu_gemm()
208 KMADD(c0, a0, b00, t0) \ in sparselu_gemm()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td395 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
400 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
405 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
410 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
415 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
420 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
427 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
429 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
434 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
439 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCInstrInfo.td482 let u5{1-0} = 0b00;
508 def LD_S_rrr : F16_LD_ADD_RR<0b00, "ld_s\t$a, [$b, $c]">;
516 def GP_LD_S : F16_GP_LD_ADD<0b00, (ins immS<11>:$s),
521 let s{1-0} = 0b00;
544 let s{1-0} = 0b00;
559 let u10{1-0} = 0b00;
573 def B_S : F16_BCC_s10<0b00, "b_s">;
594 let s13{1-0} = 0b00;
603 def ADD_S_ru3 : F16_ADD_IMM<0b00,"add_s">;
799 def _rs9 : F32_LD_ADDR<0, 0b00, 0, zz,
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td88 let Inst{3-2} = 0b00;
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
272 let Inst{3-2} = 0b00;
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
455 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
499 let Inst{27-26} = 0b00;
1069 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1073 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1078 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1082 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
[all …]
/external/clang/test/CodeGenCXX/
Dbitfield.cpp13 unsigned b00 : 14; member
35 return s->b00; in read00()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td1651 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1658 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1677 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1685 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1695 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1703 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1725 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1733 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1741 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1767 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
[all …]
DARMInstrThumb2.td602 let Inst{7-6} = 0b00; // imm2
603 let Inst{5-4} = 0b00; // type
686 let Inst{7-6} = 0b00; // imm2
687 let Inst{5-4} = 0b00; // type
807 let Inst{7-6} = 0b00; // imm2
808 let Inst{5-4} = 0b00; // type
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
947 let Inst{7-6} = 0b00; // imm2
948 let Inst{5-4} = 0b00; // type
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td1715 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1722 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1741 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1749 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1759 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1767 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1789 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1797 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1805 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1843 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
[all …]
/external/llvm/test/TableGen/
DBitsInit.td32 bits<2> D2 = { 0b00 }; // ok
34 bits<3> D4 = { 0b00 }; // type mismatch. RHS doesn't have enough bits
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DBitsInit.td32 bits<2> D2 = { 0b00 }; // ok
34 bits<3> D4 = { 0b00 }; // type mismatch. RHS doesn't have enough bits
/external/tcpdump/tests/
Dmobility_opt_asan_2.out1 … (old) (62) payload length: 7168) ff:7f0f:40:0:ee00:0:b658:5203 > 205:20:1:b00:0:2200:af01:e000: m…
Dmobility_opt_asan_5.out1 … (old) (62) payload length: 7168) ff:7f0f:40:0:ee00:0:b658:5203 > 205:20:1:b00:0:2200:af01:e000: m…

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