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Searched refs:buswidth (Results 1 – 18 of 18) sorted by relevance

/external/stressapptest/src/
Dpattern.cc286 int buswidth, in Initialize() argument
302 if (buswidth == 32) { in Initialize()
305 } else if (buswidth == 64) { in Initialize()
308 } else if (buswidth == 128) { in Initialize()
311 } else if (buswidth == 256) { in Initialize()
316 buswidth); in Initialize()
Dpattern.h55 int buswidth,
/external/u-boot/drivers/mmc/
Dmxsmmc.c33 uint32_t buswidth; member
170 ctrl0 = priv->buswidth; in mxsmmc_send_cmd()
317 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; in mxsmmc_set_ios()
320 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; in mxsmmc_set_ios()
323 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; in mxsmmc_set_ios()
329 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); in mxsmmc_set_ios()
Dftsdc010_mci.c371 static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, in ftsdc_setup_cfg() argument
379 if (buswidth == 8) { in ftsdc_setup_cfg()
397 chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in ftsdc010_mmc_ofdata_to_platdata()
436 chip->buswidth = dtplat->bus_width; in ftsdc010_mmc_probe()
449 ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps, in ftsdc010_mmc_probe()
Darm_pl180_mmci.c318 u32 buswidth = 0; in host_set_ios() local
322 buswidth |= SDI_CLKCR_WIDBUS_1; in host_set_ios()
325 buswidth |= SDI_CLKCR_WIDBUS_4; in host_set_ios()
328 buswidth |= SDI_CLKCR_WIDBUS_8; in host_set_ios()
335 sdi_clkcr |= buswidth; in host_set_ios()
Drockchip_dw_mmc.c59 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in rockchip_dwmmc_ofdata_to_platdata()
109 host->buswidth = dtplat->bus_width; in rockchip_dwmmc_probe()
Dftsdc010_mci.h30 int buswidth; member
Dhi6220_dw_mmc.c51 host->buswidth = bus_width; in hi6220_dwmci_add_port()
Dexynos_dw_mmc.c138 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; in do_dwmci_init()
175 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); in exynos_dwmci_get_config()
Dsocfpga_dw_mmc.c81 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in socfpga_dwmmc_ofdata_to_platdata()
Ddw_mmc.c503 if (host->buswidth == 8) {
/external/u-boot/arch/arm/mach-keystone/
Dddr3_spd.c137 u8 buswidth; member
186 spd->buswidth = 8 << (buf->bus_width & 0x7); in ddrtimingcalculation()
187 if ((spd->buswidth < 16) || (spd->buswidth > 64)) in ddrtimingcalculation()
372 (spd->buswidth & 3) << 12 | (spd->pagesize & 3); in init_ddr3param()
/external/u-boot/board/synopsys/axs10x/
Daxs10x.c27 host->buswidth = 4; in board_mmc_init()
/external/u-boot/board/synopsys/emdk/
Demdk.c28 host->buswidth = 4; in board_mmc_init()
/external/u-boot/include/
Ddwmmc.h160 int buswidth; member
/external/u-boot/arch/arm/dts/
Dda850-lcdk.dts272 ti,davinci-nand-buswidth = <16>;
/external/u-boot/board/synopsys/hsdk/
Dhsdk.c1041 host->buswidth = 4; in board_mmc_init()
/external/u-boot/arch/arm/mach-sunxi/
DKconfig118 have only 16-bit memory buswidth.
124 32-bit memory buswidth.