Home
last modified time | relevance | path

Searched refs:fmask (Results 1 – 25 of 65) sorted by relevance

123

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dfp16instrinsmc.ll2 …ation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask
17 ; fmask: .ent foo1
18 ; fmask: .set noreorder
19 ; fmask: .set nomacro
20 ; fmask: .set noat
21 ; fmask: .set at
22 ; fmask: .set macro
23 ; fmask: .set reorder
24 ; fmask: .end foo1
38 ; fmask: .ent foo2
[all …]
Dtnaked.ll13 ; CHECK-NOT: .fmask {{.*}}
25 ; CHECK: .fmask 0x00000000,0
/external/llvm/test/CodeGen/Mips/
Dfp16instrinsmc.ll2 …ation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask
17 ; fmask: .ent foo1
18 ; fmask: .set noreorder
19 ; fmask: .set nomacro
20 ; fmask: .set noat
21 ; fmask: .set at
22 ; fmask: .set macro
23 ; fmask: .set reorder
24 ; fmask: .end foo1
38 ; fmask: .ent foo2
[all …]
Dtnaked.ll13 ; CHECK-NOT: .fmask {{.*}}
25 ; CHECK: .fmask 0x00000000,0
/external/mesa3d/src/amd/vulkan/
Dradv_image.c499 if (image->fmask.size) { in si_make_texture_descriptor()
504 va = gpu_address + image->offset + image->fmask.offset; in si_make_texture_descriptor()
540 fmask_state[0] |= image->fmask.tile_swizzle; in si_make_texture_descriptor()
557 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode); in si_make_texture_descriptor()
559 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch); in si_make_texture_descriptor()
563 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index); in si_make_texture_descriptor()
565 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1); in si_make_texture_descriptor()
658 struct radeon_surf fmask = {}; in radv_image_get_fmask_info() local
668 fmask.blk_w = image->surface.blk_w; in radv_image_get_fmask_info()
669 fmask.blk_h = image->surface.blk_h; in radv_image_get_fmask_info()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips-pdr-bad.s29 .fmask # ASM: :[[@LINE]]:17: error: expected bitmask value
30 .fmask foo # ASM: :[[@LINE]]:20: error: bitmask not an absolute expression
31 .fmask 0x80000000 # ASM: :[[@LINE]]:27: error: unexpected token, expected comma
32 .fmask 0x80000000, # ASM: :[[@LINE]]:28: error: expected frame offset value
33 .fmask 0x80000000, foo # ASM: :[[@LINE]]:32: error: frame offset not an absolute expression
34 ….fmask 0x80000000, -4, bar # ASM: :[[@LINE]]:30: error: unexpected token, expected end of statement
Dmips-pdr.s14 # ASMOUT: .fmask 0x01010101,-8
48 .fmask 0x01010101,-8
58 .fmask 0x01010101,-8
Delf-tls.s26 .fmask 0x00000000,0
58 .fmask 0x00000000,0
90 .fmask 0x00000000,0
Dmips_gprel16.s25 .fmask 0x00000000,0
49 .fmask 0x00000000,0
Dxgot.s30 .fmask 0x00000000,0
Delf-N64.s28 .fmask 0x90000000,-4
Delf-gprel-32-64.s33 .fmask 0x00000000,0
/external/llvm/test/MC/Mips/
Dmips-pdr-bad.s29 .fmask # ASM: :[[@LINE]]:17: error: expected bitmask value
30 .fmask foo # ASM: :[[@LINE]]:20: error: bitmask not an absolute expression
31 .fmask 0x80000000 # ASM: :[[@LINE]]:27: error: unexpected token, expected comma
32 .fmask 0x80000000, # ASM: :[[@LINE]]:28: error: expected frame offset value
33 .fmask 0x80000000, foo # ASM: :[[@LINE]]:32: error: frame offset not an absolute expression
34 ….fmask 0x80000000, -4, bar # ASM: :[[@LINE]]:30: error: unexpected token, expected end of statement
Dmips-pdr.s14 # ASMOUT: .fmask 0x01010101,-8
48 .fmask 0x01010101,-8
58 .fmask 0x01010101,-8
Delf-tls.s26 .fmask 0x00000000,0
58 .fmask 0x00000000,0
90 .fmask 0x00000000,0
Dmips_gprel16.s25 .fmask 0x00000000,0
49 .fmask 0x00000000,0
Dxgot.s30 .fmask 0x00000000,0
Delf-gprel-32-64.s33 .fmask 0x00000000,0
Delf-N64.s28 .fmask 0x90000000,-4
/external/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c423 rtex->fmask = new_tex->fmask; in r600_reallocate_texture_inplace()
436 assert(!rtex->fmask.size); in r600_reallocate_texture_inplace()
582 struct radeon_surf fmask = {}; in r600_texture_get_fmask_info() local
591 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw; in r600_texture_get_fmask_info()
592 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh; in r600_texture_get_fmask_info()
593 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea; in r600_texture_get_fmask_info()
594 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split; in r600_texture_get_fmask_info()
597 fmask.u.legacy.bankh = 4; in r600_texture_get_fmask_info()
620 RADEON_SURF_MODE_2D, &fmask)) { in r600_texture_get_fmask_info()
625 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in r600_texture_get_fmask_info()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_texture.c554 rtex->fmask = new_tex->fmask; in r600_reallocate_texture_inplace()
568 assert(!rtex->fmask.size); in r600_reallocate_texture_inplace()
602 assert(rtex->fmask.size == 0); in si_query_opaque_metadata()
841 struct radeon_surf fmask = {}; in si_texture_get_fmask_info() local
869 RADEON_SURF_MODE_2D, &fmask)) { in si_texture_get_fmask_info()
874 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in si_texture_get_fmask_info()
876 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in si_texture_get_fmask_info()
880 out->tile_mode_index = fmask.u.legacy.tiling_index[0]; in si_texture_get_fmask_info()
881 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; in si_texture_get_fmask_info()
882 out->bank_height = fmask.u.legacy.bankh; in si_texture_get_fmask_info()
[all …]
/external/ltp/testcases/kernel/syscalls/sched_setaffinity/
Dsched_setaffinity01.c51 static cpu_set_t *fmask = (void *)-1; variable
65 {&self_pid, &mask_size, &fmask, EFAULT},
/external/mesa3d/src/amd/common/
Dac_surface.c566 AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0; in gfx6_compute_surface()
575 !AddrSurfInfoIn.flags.fmask && in gfx6_compute_surface()
840 sin.flags.fmask = 1; in gfx9_get_preferred_swizzle_mode()
883 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; in gfx9_compute_miptree()
884 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch; in gfx9_compute_miptree()
1017 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode; in gfx9_compute_miptree()
1018 surf->u.gfx9.fmask.epitch = fout.pitch - 1; in gfx9_compute_miptree()
1040 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode; in gfx9_compute_miptree()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.c2441 if (rtex->fmask.size) { in si_initialize_color_surface()
2443 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); in si_initialize_color_surface()
2476 if (!rtex->fmask.size && sctx->b.chip_class == SI) { in si_initialize_color_surface()
2691 if (rtex->fmask.size) in si_update_fb_dirtiness_after_rendering()
2863 if (rtex->fmask.size) { in si_set_framebuffer_state()
3008 if (tex->fmask.size) { in si_emit_framebuffer_state()
3009 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8; in si_emit_framebuffer_state()
3010 cb_color_fmask |= tex->fmask.tile_swizzle; in si_emit_framebuffer_state()
3039 if (!tex->fmask.size) in si_emit_framebuffer_state()
3042 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) | in si_emit_framebuffer_state()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/ExecutionEngine/RuntimeDyld/Mips/
DELF_N32_relocations.s34 .fmask 0x00000000,0
82 .fmask 0x00000000,0

123