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Searched refs:ft0 (Results 1 – 25 of 38) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
Dfloat-select-fcmp.ll19 ; RV32IF-NEXT: fmv.w.x ft0, a0
20 ; RV32IF-NEXT: feq.s a0, ft0, ft1
23 ; RV32IF-NEXT: fmv.s ft0, ft1
25 ; RV32IF-NEXT: fmv.x.w a0, ft0
35 ; RV32IF-NEXT: fmv.w.x ft0, a0
37 ; RV32IF-NEXT: flt.s a0, ft1, ft0
40 ; RV32IF-NEXT: fmv.s ft0, ft1
42 ; RV32IF-NEXT: fmv.x.w a0, ft0
52 ; RV32IF-NEXT: fmv.w.x ft0, a0
54 ; RV32IF-NEXT: fle.s a0, ft1, ft0
[all …]
Dfloat-arith.ll8 ; RV32IF-NEXT: fmv.w.x ft0, a1
10 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
11 ; RV32IF-NEXT: fmv.x.w a0, ft0
20 ; RV32IF-NEXT: fmv.w.x ft0, a1
22 ; RV32IF-NEXT: fsub.s ft0, ft1, ft0
23 ; RV32IF-NEXT: fmv.x.w a0, ft0
32 ; RV32IF-NEXT: fmv.w.x ft0, a1
34 ; RV32IF-NEXT: fmul.s ft0, ft1, ft0
35 ; RV32IF-NEXT: fmv.x.w a0, ft0
44 ; RV32IF-NEXT: fmv.w.x ft0, a1
[all …]
Dfloat-fcmp.ll18 ; RV32IF-NEXT: fmv.w.x ft0, a1
20 ; RV32IF-NEXT: feq.s a0, ft1, ft0
30 ; RV32IF-NEXT: fmv.w.x ft0, a0
32 ; RV32IF-NEXT: flt.s a0, ft1, ft0
42 ; RV32IF-NEXT: fmv.w.x ft0, a0
44 ; RV32IF-NEXT: fle.s a0, ft1, ft0
54 ; RV32IF-NEXT: fmv.w.x ft0, a1
56 ; RV32IF-NEXT: flt.s a0, ft1, ft0
66 ; RV32IF-NEXT: fmv.w.x ft0, a1
68 ; RV32IF-NEXT: fle.s a0, ft1, ft0
[all …]
Ddouble-arith.ll11 ; RV32IFD-NEXT: fld ft0, 8(sp)
15 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
16 ; RV32IFD-NEXT: fsd ft0, 8(sp)
31 ; RV32IFD-NEXT: fld ft0, 8(sp)
35 ; RV32IFD-NEXT: fsub.d ft0, ft1, ft0
36 ; RV32IFD-NEXT: fsd ft0, 8(sp)
51 ; RV32IFD-NEXT: fld ft0, 8(sp)
55 ; RV32IFD-NEXT: fmul.d ft0, ft1, ft0
56 ; RV32IFD-NEXT: fsd ft0, 8(sp)
71 ; RV32IFD-NEXT: fld ft0, 8(sp)
[all …]
Dfloat-mem.ll8 ; RV32IF-NEXT: flw ft0, 12(a0)
10 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
11 ; RV32IF-NEXT: fmv.x.w a0, ft0
27 ; RV32IF-NEXT: fmv.w.x ft0, a2
29 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
30 ; RV32IF-NEXT: fsw ft0, 32(a0)
31 ; RV32IF-NEXT: fsw ft0, 0(a0)
48 ; RV32IF-NEXT: fmv.w.x ft0, a1
50 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
53 ; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
[all …]
Ddouble-mem.ll9 ; RV32IFD-NEXT: fld ft0, 24(a0)
11 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
12 ; RV32IFD-NEXT: fsd ft0, 8(sp)
32 ; RV32IFD-NEXT: fld ft0, 8(sp)
36 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
37 ; RV32IFD-NEXT: fsd ft0, 64(a0)
38 ; RV32IFD-NEXT: fsd ft0, 0(a0)
59 ; RV32IFD-NEXT: fld ft0, 8(sp)
63 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
66 ; RV32IFD-NEXT: fsd ft0, %lo(G)(a0)
[all …]
Dfloat-convert.ll8 ; RV32IF-NEXT: fmv.w.x ft0, a0
9 ; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
18 ; RV32IF-NEXT: fmv.w.x ft0, a0
19 ; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
28 ; RV32IF-NEXT: fmv.w.x ft0, a1
30 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
31 ; RV32IF-NEXT: fmv.x.w a0, ft0
42 ; RV32IF-NEXT: fcvt.s.w ft0, a0
43 ; RV32IF-NEXT: fmv.x.w a0, ft0
52 ; RV32IF-NEXT: fcvt.s.wu ft0, a0
[all …]
Ddouble-select-fcmp.ll22 ; RV32IFD-NEXT: fld ft0, 8(sp)
26 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
29 ; RV32IFD-NEXT: fmv.d ft1, ft0
47 ; RV32IFD-NEXT: fld ft0, 8(sp)
51 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
54 ; RV32IFD-NEXT: fmv.d ft0, ft1
56 ; RV32IFD-NEXT: fsd ft0, 8(sp)
72 ; RV32IFD-NEXT: fld ft0, 8(sp)
76 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
79 ; RV32IFD-NEXT: fmv.d ft0, ft1
[all …]
Ddouble-convert.ll11 ; RV32IFD-NEXT: fld ft0, 8(sp)
12 ; RV32IFD-NEXT: fcvt.s.d ft0, ft0
13 ; RV32IFD-NEXT: fmv.x.w a0, ft0
24 ; RV32IFD-NEXT: fmv.w.x ft0, a0
25 ; RV32IFD-NEXT: fcvt.d.s ft0, ft0
26 ; RV32IFD-NEXT: fsd ft0, 8(sp)
41 ; RV32IFD-NEXT: fld ft0, 8(sp)
42 ; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
55 ; RV32IFD-NEXT: fld ft0, 8(sp)
56 ; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
[all …]
Ddouble-fcmp.ll21 ; RV32IFD-NEXT: fld ft0, 8(sp)
25 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
39 ; RV32IFD-NEXT: fld ft0, 8(sp)
43 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
57 ; RV32IFD-NEXT: fld ft0, 8(sp)
61 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
75 ; RV32IFD-NEXT: fld ft0, 8(sp)
79 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
93 ; RV32IFD-NEXT: fld ft0, 8(sp)
97 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
[all …]
Dfloat-br-fcmp.ll36 ; RV32IF-NEXT: fmv.w.x ft0, a1
38 ; RV32IF-NEXT: feq.s a0, ft1, ft0
63 ; RV32IF-NEXT: fmv.w.x ft0, a1
65 ; RV32IF-NEXT: feq.s a0, ft1, ft0
88 ; RV32IF-NEXT: fmv.w.x ft0, a0
90 ; RV32IF-NEXT: flt.s a0, ft1, ft0
112 ; RV32IF-NEXT: fmv.w.x ft0, a0
114 ; RV32IF-NEXT: fle.s a0, ft1, ft0
136 ; RV32IF-NEXT: fmv.w.x ft0, a1
138 ; RV32IF-NEXT: flt.s a0, ft1, ft0
[all …]
Ddouble-calling-conv.ll16 ; RV32IFD-NEXT: fld ft0, 8(sp)
20 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
21 ; RV32IFD-NEXT: fsd ft0, 8(sp)
39 ; RV32IFD-NEXT: fld ft0, 0(a0)
46 ; RV32IFD-NEXT: fsd ft0, 0(sp)
64 ; RV32IFD-NEXT: fld ft0, 8(sp)
68 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
69 ; RV32IFD-NEXT: fsd ft0, 8(sp)
85 ; RV32IFD-NEXT: fld ft0, 0(a0)
86 ; RV32IFD-NEXT: fsd ft0, 16(sp)
[all …]
Dinterrupt-attr-nocall.ll93 ; CHECK-RV32-F-NEXT: fsw ft0, 8(sp)
96 ; CHECK-RV32-F-NEXT: flw ft0, %lo(f)(a0)
99 ; CHECK-RV32-F-NEXT: fadd.s ft0, ft1, ft0
101 ; CHECK-RV32-F-NEXT: fsw ft0, %lo(d)(a0)
103 ; CHECK-RV32-F-NEXT: flw ft0, 8(sp)
125 ; CHECK-RV32-F-NEXT: fsw ft0, 16(sp)
129 ; CHECK-RV32-F-NEXT: flw ft0, %lo(f)(a0)
132 ; CHECK-RV32-F-NEXT: fadd.s ft0, ft1, ft0
134 ; CHECK-RV32-F-NEXT: fsw ft0, %lo(d)(a0)
136 ; CHECK-RV32-F-NEXT: flw ft0, 16(sp)
[all …]
Ddouble-br-fcmp.ll37 ; RV32IFD-NEXT: fld ft0, 0(sp)
41 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
68 ; RV32IFD-NEXT: fld ft0, 0(sp)
72 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
97 ; RV32IFD-NEXT: fld ft0, 0(sp)
101 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
125 ; RV32IFD-NEXT: fld ft0, 0(sp)
129 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
153 ; RV32IFD-NEXT: fld ft0, 0(sp)
157 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
[all …]
Ddouble-stack-spill-restore.ll12 ; RV32IFD-NEXT: fld ft0, 16(sp)
16 ; RV32IFD-NEXT: fsd ft0, 16(sp)
19 ; RV32IFD-NEXT: fsd ft0, 8(sp)
23 ; RV32IFD-NEXT: fld ft0, 16(sp)
25 ; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
27 ; RV32IFD-NEXT: fsd ft0, 16(sp)
Ddouble-imm.ll11 ; RV32IFD-NEXT: fld ft0, 0(a0)
12 ; RV32IFD-NEXT: fsd ft0, 8(sp)
26 ; RV32IFD-NEXT: fld ft0, 8(sp)
30 ; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
31 ; RV32IFD-NEXT: fsd ft0, 8(sp)
Dfloat-imm.ll18 ; RV32IF-NEXT: fmv.w.x ft0, a0
22 ; RV32IF-NEXT: fadd.s ft0, ft0, ft1
23 ; RV32IF-NEXT: fmv.x.w a0, ft0
Ddouble-previous-failure.ll22 ; RV32IFD-NEXT: fld ft0, 0(a0)
23 ; RV32IFD-NEXT: fsd ft0, 0(sp)
32 ; RV32IFD-NEXT: fld ft0, 0(sp)
33 ; RV32IFD-NEXT: flt.d a0, ft0, ft1
39 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Dcompress-rv32f.s13 flw ft0, 124(sp)
15 # CHECK-ALIAS: flw ft0, 124(sp)
16 # CHECK-INST: c.flwsp ft0, 124(sp)
18 fsw ft0, 124(sp)
20 # CHECK-ALIAS: fsw ft0, 124(sp)
21 # CHECK-INST: c.fswsp ft0, 124(sp)
Dcompress-rv32d.s25 fld ft0, 64(sp)
27 # CHECK-ALIAS: fld ft0, 64(sp)
28 # CHECK-INST: c.fldsp ft0, 64(sp)
30 fsd ft0, 64(sp)
32 # CHECK-ALIAS: fsd ft0, 64(sp)
33 # CHECK-INST: c.fsdsp ft0, 64(sp)
Drv32f-valid.s12 # CHECK-INST: flw ft0, 12(a0)
63 # CHECK-INST: fmul.s ft0, ft1, ft2, dyn
65 fmul.s ft0, ft1, ft2, dyn
111 # CHECK-INST: fcvt.s.wu ft0, a5, dyn
113 fcvt.s.wu ft0, a5, dyn
145 # CHECK-INST: fmul.s ft0, ft1, ft2, rdn
147 fmul.s ft0, ft1, ft2, rdn
164 # CHECK-INST: fcvt.s.wu ft0, a5, rne
166 fcvt.s.wu ft0, a5, rne
Drvf-aliases-valid.s29 # CHECK-INST: fsgnj.s ft0, ft1, ft1
30 # CHECK-ALIAS: fmv.s ft0, ft1
119 # CHECK-INST: fmul.s ft0, ft1, ft2, dyn
120 # CHECK-ALIAS: fmul.s ft0, ft1, ft2{{[[:space:]]}}
121 fmul.s ft0, ft1, ft2
137 # CHECK-INST: fcvt.s.wu ft0, a5, dyn
138 # CHECK-ALIAS: fcvt.s.wu ft0, a5{{[[:space:]]}}
139 fcvt.s.wu ft0, a5
Drv32d-valid.s17 # CHECK-INST: fld ft0, 12(a0)
68 # CHECK-INST: fmul.d ft0, ft1, ft2, dyn
70 fmul.d ft0, ft1, ft2, dyn
115 # CHECK-INST: fcvt.d.w ft0, a5
117 fcvt.d.w ft0, a5
143 # CHECK-INST: fmul.d ft0, ft1, ft2, rne
145 fmul.d ft0, ft1, ft2, rne
Drv64d-valid.s9 # CHECK-INST: fcvt.l.d a0, ft0, dyn
12 fcvt.l.d a0, ft0, dyn
43 # CHECK-INST: fcvt.l.d a0, ft0, rdn
46 fcvt.l.d a0, ft0, rdn
Drv64f-aliases-valid.s16 # CHECK-INST: fcvt.l.s a0, ft0, dyn
17 # CHECK-ALIAS: fcvt.l.s a0, ft0{{[[:space:]]}}
18 fcvt.l.s a0, ft0

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