| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 200 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { in getRawAllocationOrder() function
512 getRawAllocationOrder(const TargetRegisterClass *RC, in getRawAllocationOrder() function
515 return RC->getRawAllocationOrder(MF); in getRawAllocationOrder()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AllocationOrder.cpp | 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, in AllocationOrder()
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| D | RegisterClassInfo.cpp | 84 ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
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| D | RegAllocPBQP.cpp | 227 ArrayRef<unsigned> rawOrder = trc->getRawAllocationOrder(*mf); in build()
587 physReg = liRC->getRawAllocationOrder(*mf).front(); in finalizeAlloc()
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| D | RenderMachineFunction.cpp | 437 unsigned capacity = trc->getRawAllocationOrder(*mf).size(); in initCapacity()
484 if (trc->getRawAllocationOrder(*mf).empty()) in resetPressureAndLiveStates()
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| D | RegAllocLinearScan.cpp | 1435 Order = tri_->getRawAllocationOrder(RC, Hint.first, physReg, *mf_); in getFreePhysReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 420 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, in getRawAllocationOrder() function in ARMBaseRegisterInfo
499 return RC->getRawAllocationOrder(MF); in getRawAllocationOrder()
505 return RC->getRawAllocationOrder(MF); in getRawAllocationOrder()
527 return RC->getRawAllocationOrder(MF); in getRawAllocationOrder()
546 return RC->getRawAllocationOrder(MF); in getRawAllocationOrder()
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| D | ARMBaseRegisterInfo.h | 128 ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC,
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| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
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| D | TargetRegisterInfo.cpp | 150 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC()
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| D | RegAllocPBQP.cpp | 585 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
717 PReg = RC.getRawAllocationOrder(MF).front(); in finalizeAlloc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 109 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
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| D | RegAllocPBQP.cpp | 613 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
758 const ArrayRef<MCPhysReg> RawPRegOrder = RC.getRawAllocationOrder(MF); in finalizeAlloc()
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| D | TargetRegisterInfo.cpp | 212 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC()
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| D | RegisterScavenging.cpp | 585 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); in scavengeRegisterBackwards()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 224 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { in getRawAllocationOrder() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 188 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { in getRawAllocationOrder() function
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1845 for (unsigned Reg : RC->getRawAllocationOrder(MF)) { in findPhysReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1964 for (unsigned Reg : RC->getRawAllocationOrder(MF)) { in findPhysReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 2453 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
2529 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const;
3394 ArrayRef<unsigned> GR8Class::getRawAllocationOrder(const MachineFunction &MF) const {
3426 ArrayRef<unsigned> GR8_NOREXClass::getRawAllocationOrder(const MachineFunction &MF) const {
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