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Searched refs:getSubReg (Results 1 – 25 of 245) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitPrologue()
110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitPrologue()
227 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitPrologue()
228 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3); in emitPrologue()
230 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1); in emitPrologue()
231 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3); in emitPrologue()
240 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitPrologue()
241 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitPrologue()
242 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitPrologue()
243 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitPrologue()
DSIFoldOperands.cpp113 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
222 if (FoldRC->getSize() == 8 && UseOp.getSubReg()) { in foldOperand()
226 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
229 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
264 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
DR600ExpandSpecialInstrs.cpp187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp465 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
792 SrcSubReg = MOSrc.getSubReg(); in getNextRewritableSource()
796 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
860 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNewSource()
916 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
992 SrcSubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource()
998 if (MODef.getSubReg()) in getNextRewritableSource()
1041 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1049 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
1119 if ((SrcSubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
[all …]
DDetectDeadLanes.cpp165 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
204 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
300 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
349 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
401 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
415 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
DCalcSpillWeights.cpp51 sub = mi->getOperand(0).getSubReg(); in copyHint()
53 hsub = mi->getOperand(1).getSubReg(); in copyHint()
55 sub = mi->getOperand(1).getSubReg(); in copyHint()
57 hsub = mi->getOperand(0).getSubReg(); in copyHint()
DTargetRegisterInfo.cpp218 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
257 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
266 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
276 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
277 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
846 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
849 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
892 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
929 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
934 if (MODef.getSubReg()) in getNextRewritableSource()
977 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
985 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1064 return MODef.getSubReg() == 0; in getNextRewritableSource()
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DCalcSpillWeights.cpp57 sub = mi->getOperand(0).getSubReg(); in copyHint()
59 hsub = mi->getOperand(1).getSubReg(); in copyHint()
61 sub = mi->getOperand(1).getSubReg(); in copyHint()
63 hsub = mi->getOperand(0).getSubReg(); in copyHint()
82 unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); in copyHint()
DDetectDeadLanes.cpp163 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
202 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
298 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
347 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
399 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
413 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
428 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
461 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DProcessImplicitDefs.cpp53 return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 || in CanTurnIntoImplicitDef()
56 return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 || in CanTurnIntoImplicitDef()
69 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg())) in isUndefCopy()
108 if (MI->getOperand(0).getSubReg()) in runOnMachineFunction()
121 if (MI->isCopy() && MI->getOperand(0).getSubReg()) { in runOnMachineFunction()
143 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef()) in runOnMachineFunction()
DCalcSpillWeights.cpp64 sub = mi->getOperand(0).getSubReg(); in copyHint()
66 hsub = mi->getOperand(1).getSubReg(); in copyHint()
68 sub = mi->getOperand(1).getSubReg(); in copyHint()
70 hsub = mi->getOperand(0).getSubReg(); in copyHint()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp204 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
324 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
336 if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
352 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
407 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()
418 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
421 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
512 if (Op.getSubReg() != AMDGPU::NoSubRegister || in getImmOrMaterializedImm()
784 Src0->getSubReg() != Src1->getSubReg() || in isClamp()
785 Src0->getSubReg() != AMDGPU::NoSubRegister) in isClamp()
[all …]
DR600ExpandSpecialInstrs.cpp224 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
225 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
230 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
231 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
239 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIFrameLowering.cpp67 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitFlatScratchInit()
68 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitFlatScratchInit()
380 unsigned RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
381 unsigned RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
382 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
439 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchSetup()
440 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchSetup()
446 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
474 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
475 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp237 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
306 if (!Op.getSubReg()) in profit()
310 if (MI->getOperand(1).getSubReg() != 0) in profit()
398 if (Op.getSubReg()) in isProfitable()
561 unsigned SR = Op.getSubReg(); in createHalfInstr()
608 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
611 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
617 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
633 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
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DHexagonRDFOpt.cpp108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in interpretAsCopy()
110 { HiOp.getReg(), HiOp.getSubReg() }); in interpretAsCopy()
112 { LoOp.getReg(), LoOp.getSubReg() }); in interpretAsCopy()
124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() }, in interpretAsCopy()
125 { SrcOp.getReg(), SrcOp.getSubReg() }); in interpretAsCopy()
DHexagonAsmPrinter.cpp413 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
414 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
501 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
502 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
513 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
514 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
526 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
527 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
DHexagonRDF.cpp53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg); in covers()
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg); in covers()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp260 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
322 if (!Op.getSubReg()) in profit()
326 if (MI->getOperand(1).getSubReg() != 0) in profit()
445 if (Op.getSubReg()) in isProfitable()
608 unsigned SR = Op.getSubReg(); in createHalfInstr()
654 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
657 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
663 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
667 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
679 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
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DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp440 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
441 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
442 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
443 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
445 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
446 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
447 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
448 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
450 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
451 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
158 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
160 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp145 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
147 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
149 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
151 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
153 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp183 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
184 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
195 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
196 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()

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