| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 4828 unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1)…
4832 return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4835 return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4840 unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1)…
4842 case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
4849 …gned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4853 return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4858 …ned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4862 return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4867 …ned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 12051 unsigned fastEmit_ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
12054 return fastEmitInst_ri(X86::ADD8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
12057 unsigned fastEmit_ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
12060 return fastEmitInst_ri(X86::ADD16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
12063 unsigned fastEmit_ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
12066 return fastEmitInst_ri(X86::ADD32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
12069 unsigned fastEmit_ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
12071 case MVT::i8: return fastEmit_ISD_ADD_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1);
12072 case MVT::i16: return fastEmit_ISD_ADD_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1);
12073 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenFastISel.inc | 4091 unsigned FastEmit_ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4094 return FastEmitInst_ri(X86::ADD8ri, X86::GR8RegisterClass, Op0, Op0IsKill, imm1);
4097 unsigned FastEmit_ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4100 return FastEmitInst_ri(X86::ADD16ri, X86::GR16RegisterClass, Op0, Op0IsKill, imm1);
4103 unsigned FastEmit_ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4106 return FastEmitInst_ri(X86::ADD32ri, X86::GR32RegisterClass, Op0, Op0IsKill, imm1);
4109 unsigned FastEmit_ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4111 case MVT::i8: return FastEmit_ISD_ADD_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1);
4112 case MVT::i16: return FastEmit_ISD_ADD_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1);
4113 case MVT::i32: return FastEmit_ISD_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
[all …]
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| D | README-SSE.txt | 502 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenFastISel.inc | 7431 …ANE64_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
7435 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1);
7440 …ANE64_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
7443 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1);
7446 …PLANE64_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
7448 …urn fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1);
7449 …urn fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1);
7456 …R_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
7460 return fastEmitInst_ri(AArch64::UMOVvi64, &AArch64::GPR64RegClass, Op0, Op0IsKill, imm1);
7465 …R_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenFastISel.inc | 3440 …Emit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3444 return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3447 return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3452 …Emit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3454 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
3461 …ned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3465 return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3470 …ed fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3474 return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3479 …gned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
[all …]
|
| /external/mesa3d/src/compiler/glsl/ |
| D | lower_blend_equation_advanced.cpp | 35 #define imm1(x) new(mem_ctx) ir_constant((float) (x), 1) macro
228 f->emit(if_tree(less(mincol, imm1(0)), in set_lum()
231 if_tree(greater(maxcol, imm1(1)), in set_lum()
262 f->emit(if_tree(greater(sbase, imm1(0)), in set_lum_sat()
310 f.emit(if_tree(equal(dst_alpha, imm1(0)), in calc_blend_result()
318 f.emit(if_tree(equal(src_alpha, imm1(0)), in calc_blend_result()
406 f.emit(assign(p1, mul(src_alpha, sub(imm1(1), dst_alpha)))); in calc_blend_result()
407 f.emit(assign(p2, mul(dst_alpha, sub(imm1(1), src_alpha)))); in calc_blend_result()
|
| /external/u-boot/post/lib_powerpc/ |
| D | cpu_asm.h | 162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument
167 ((imm1) << 6) + \
169 #define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ argument
173 ((imm1) << 11) + \
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 520 ImmediateValue &imm0, ImmediateValue &imm1) in expr() argument
522 struct Storage *const a = &imm0.reg, *const b = &imm1.reg; in expr()
741 ImmediateValue &imm1, in expr() argument
744 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
848 ImmediateValue imm1; in tryCollapseChainedMULs() local
859 if (mul1->src(s1 = 0).getImmediate(imm1) || in tryCollapseChainedMULs()
860 mul1->src(s1 = 1).getImmediate(imm1)) { in tryCollapseChainedMULs()
864 mul1->setSrc(s1, bld.loadImm(NULL, f * imm1.reg.data.f32)); in tryCollapseChainedMULs()
893 if (!insn->src(s2).mod && !insn->src(t2).getImmediate(imm1)) in tryCollapseChainedMULs()
1267 ImmediateValue imm1; in opnd() local
[all …]
|
| /external/v8/src/wasm/ |
| D | wasm-module-builder.cc | 96 void WasmFunctionBuilder::EmitWithU8U8(WasmOpcode opcode, const byte imm1, in EmitWithU8U8() argument
99 body_.write_u8(imm1); in EmitWithU8U8()
|
| D | wasm-module-builder.h | 171 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 1193 sljit_uw imm1; in generate_int() local
1236 imm1 = SRC2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8); in generate_int()
1240 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1275 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1295 FAIL_IF(push_inst(compiler, (positive ? MOV : MVN) | RD(reg) | imm1)); in generate_int()
|
| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 217 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2790 for (unsigned imm1 = 0; imm1 < inputs_imm1_length; imm1++) { in TestOpImmOpImmNEON() local
2799 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2826 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2831 unsigned input_index_imm1 = imm1; in TestOpImmOpImmNEON()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 2109 int64_t imm1 = in AssembleArchInstruction() local
2115 __ Movi(temp, imm2, imm1); in AssembleArchInstruction()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 187 unsigned Op0, bool Op0IsKill, uint64_t imm1, in fastEmitInst_riir() argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 235 unsigned Op0, bool Op0IsKill, uint64_t imm1, in fastEmitInst_riir() argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFormats.td | 2969 Immediate imm1, Immediate imm2>
2970 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 80 def imm1 : NVPTXInst<
954 def imm1 : NVPTXInst<(outs regclass:$dst),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 118 def imm1 : NVPTXInst<
1076 def imm1 : NVPTXInst<(outs regclass:$dst),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4318 // SETPAN #imm1
|
| D | ARMInstrInfo.td | 4587 // SETPAN #imm1
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4320 // SETPAN #imm1
|
| D | ARMInstrInfo.td | 4338 // SETPAN #imm1
|