| /external/v8/src/mips/ |
| D | assembler-mips.h | 1146 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
1147 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
1148 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
1149 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
1150 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
1151 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
1152 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
1153 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
1154 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
1155 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
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| D | assembler-mips.cc | 1347 int32_t imm5, MSARegister ws, MSARegister wd) { in GenInstrMsaI5() argument
1353 ? is_int5(imm5) in GenInstrMsaI5()
1354 : is_uint5(imm5)); in GenInstrMsaI5()
1355 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) | in GenInstrMsaI5()
3315 uint32_t imm5) { \
3316 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
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| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 1218 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
1219 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
1220 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
1221 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
1222 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
1223 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
1224 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
1225 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
1226 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
1227 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
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| D | assembler-mips64.cc | 1311 int32_t imm5, MSARegister ws, MSARegister wd) { in GenInstrMsaI5() argument
1317 ? is_int5(imm5) in GenInstrMsaI5()
1318 : is_uint5(imm5)); in GenInstrMsaI5()
1319 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) | in GenInstrMsaI5()
3632 uint32_t imm5) { \
3633 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 168 // t_addrmode_is4 := reg + imm5 * 4
180 // t_addrmode_is2 := reg + imm5 * 2
192 // t_addrmode_is1 := reg + imm5
575 // Loads: reg/reg and reg/imm5
587 def i : // reg/imm5
593 // Stores: reg/reg and reg/imm5
604 def i : // reg/imm5
909 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
911 "asr", "\t$Rd, $Rm, $imm5",
912 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
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| D | ARMInstrFormats.td | 1021 let Inst{10-6} = addr{7-3}; // imm5
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| D | ARMInstrInfo.td | 437 // {4-0} imm5 shift amount.
438 // asr #32 encoded as imm5 == 0.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 214 // t_addrmode_is4 := reg + imm5 * 4
226 // t_addrmode_is2 := reg + imm5 * 2
238 // t_addrmode_is1 := reg + imm5
658 // Loads: reg/reg and reg/imm5
668 def i : // reg/imm5
680 // Stores: reg/reg and reg/imm5
686 def i : // reg/imm5
962 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
964 "asr", "\t$Rd, $Rm, $imm5",
965 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 223 // t_addrmode_is4 := reg + imm5 * 4
235 // t_addrmode_is2 := reg + imm5 * 2
247 // t_addrmode_is1 := reg + imm5
675 // Loads: reg/reg and reg/imm5
685 def i : // reg/imm5
697 // Stores: reg/reg and reg/imm5
703 def i : // reg/imm5
1036 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1038 "asr", "\t$Rd, $Rm, $imm5",
1039 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 2145 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
2146 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
2152 bits<5> imm5;
2156 let Inst{20-16} = imm5;
2403 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
2404 asm, "\t$Zd, $imm5, $imm5b",
2407 bits<5> imm5;
2414 let Inst{9-5} = imm5;
2427 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
2428 asm, "\t$Zd, $imm5, $Rm",
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-MVN-arm.txt | 8 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm |
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFormats.td | 167 bits<5> imm5;
174 let Inst{27-31} = imm5;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
238 bits<5> imm5;
245 let Inst{4-0} = imm5;
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| D | Mips64InstrInfo.td | 848 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
850 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
854 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
856 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
860 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
862 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
238 bits<5> imm5;
245 let Inst{4-0} = imm5;
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | README.txt | 80 | Ks5 | imm5 | |
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 3747 static Instr ImmPrefetchOperation(int imm5) { in ImmPrefetchOperation() argument
3748 VIXL_ASSERT(IsUint5(imm5)); in ImmPrefetchOperation()
3749 return imm5 << ImmPrefetchOperation_offset; in ImmPrefetchOperation()
4029 int imm5 = (index << (s + 1)) | (1 << s); in ImmNEON5() local
4030 return imm5 << ImmNEON5_offset; in ImmNEON5()
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| D | simulator-aarch64.cc | 4937 int imm5 = instr->GetImmNEON5(); in VisitNEONCopy() local
4938 int tz = CountTrailingZeros(imm5, 32); in VisitNEONCopy()
4939 int reg_index = imm5 >> (tz + 1); in VisitNEONCopy()
5996 int imm5 = instr->GetImmNEON5(); in VisitNEONScalarCopy() local
5997 int tz = CountTrailingZeros(imm5, 32); in VisitNEONScalarCopy()
5998 int rn_index = imm5 >> (tz + 1); in VisitNEONScalarCopy()
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| D | disasm-aarch64.cc | 5282 unsigned imm5 = instr->GetImmNEON5(); in SubstituteImmediateField() local
5284 int tz = CountTrailingZeros(imm5, 32); in SubstituteImmediateField()
5286 rd_index = imm5 >> (tz + 1); in SubstituteImmediateField()
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| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 4336 int imm5 = instr->ImmNEON5(); in VisitNEONCopy() local
4337 int lsb = LowestSetBitPosition(imm5); in VisitNEONCopy()
4338 int reg_index = imm5 >> lsb; in VisitNEONCopy()
5213 int imm5 = instr->ImmNEON5(); in VisitNEONScalarCopy() local
5214 int lsb = LowestSetBitPosition(imm5); in VisitNEONScalarCopy()
5215 int rn_index = imm5 >> lsb; in VisitNEONScalarCopy()
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| D | disasm-arm64.cc | 3704 unsigned imm5 = instr->ImmNEON5(); in SubstituteImmediateField() local
3706 int tz = CountTrailingZeros(imm5, 32); in SubstituteImmediateField()
3708 rd_index = imm5 >> (tz + 1); in SubstituteImmediateField()
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| D | assembler-arm64.h | 3107 int imm5 = (index << (s + 1)) | (1 << s); in ImmNEON5() local
3108 return imm5 << ImmNEON5_offset; in ImmNEON5()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 335 IOffsetT imm5) { in encodeShiftRotateImm5() argument
337 assert(imm5 < (1 << kShiftImmBits)); in encodeShiftRotateImm5()
338 return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm; in encodeShiftRotateImm5()
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 3181 int imm5 = 32 - fraction_bits; in vcvt_f64_s32() local
3182 int i = imm5 & 1; in vcvt_f64_s32()
3183 int imm4 = (imm5 >> 1) & 0xF; in vcvt_f64_s32()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 4839 // op: imm5
5958 // op: imm5
5977 // op: imm5
5995 // op: imm5
9251 // op: imm5
9412 // op: imm5
11307 // op: imm5
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