| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 284 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1534 bool is64BitVector) { in GetVLDSTAlign() argument
1536 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1565 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1566 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVLD()
1592 if (!is64BitVector) in SelectVLD()
1608 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1609 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1666 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1693 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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| D | ARMISelLowering.cpp | 3821 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
3849 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
3872 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
3898 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
4188 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
4671 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
4672 Op1.getValueType().is64BitVector() && in LowerMUL()
6626 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
7286 if (!VT.is64BitVector()) in CombineVLDDUP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 245 bool is64BitVector);
1603 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1605 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1759 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1760 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
1785 if (!is64BitVector) in SelectVLD()
1801 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1802 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1871 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1901 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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| D | ARMISelLowering.cpp | 5413 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTTZ()
5418 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in LowerCTTZ()
5425 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32; in LowerCTTZ()
5463 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
5486 if (VT.is64BitVector()) { in lowerCTPOP16BitElements()
5520 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in lowerCTPOP32BitElements()
5528 if (VT.is64BitVector()) { in lowerCTPOP32BitElements()
6281 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
6317 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
6355 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 148 bool is64BitVector() const { in is64BitVector() function
149 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
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| D | MachineValueType.h | 240 bool is64BitVector() const { in is64BitVector() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 177 bool is64BitVector() const { in is64BitVector() function
178 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 269 bool is64BitVector);
1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1690 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1822 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1823 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
1850 if (!is64BitVector) in SelectVLD()
1866 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1867 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1934 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1962 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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| D | ARMISelLowering.cpp | 4656 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTTZ()
4661 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in LowerCTTZ()
4668 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32; in LowerCTTZ()
4706 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
4729 if (VT.is64BitVector()) { in lowerCTPOP16BitElements()
4763 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in lowerCTPOP32BitElements()
4771 if (VT.is64BitVector()) { in lowerCTPOP32BitElements()
5473 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
5509 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
5547 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
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| D | AArch64ISelLowering.cpp | 2604 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
2605 Op1.getValueType().is64BitVector() && in LowerMUL()
3020 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
7354 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9372 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
9589 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
9590 RHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
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| D | AArch64FastISel.cpp | 2951 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2995 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
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| D | AArch64ISelDAGToDAG.cpp | 1157 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
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| D | AArch64ISelLowering.cpp | 2262 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
2263 Op1.getValueType().is64BitVector() && in LowerMUL()
2517 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
6545 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
8207 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
8424 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
8425 RHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
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| D | AArch64FastISel.cpp | 2865 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2909 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
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| D | AArch64ISelDAGToDAG.cpp | 1100 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ValueTypes.h | 484 bool is64BitVector() const { in is64BitVector() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 343 bool is64BitVector() const { in is64BitVector() function
|