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Searched refs:isInConsecutiveRegs (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp317 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
409 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
461 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
489 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetCallingConv.h102 bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; } in isInConsecutiveRegs() function
/external/llvm/include/llvm/Target/
DTargetCallingConv.h100 bool isInConsecutiveRegs() const { return Flags & InConsecutiveRegs; } in isInConsecutiveRegs() function
DTargetCallingConv.td57 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp507 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
599 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
651 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
679 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetCallingConv.td57 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc118 if (ArgFlags.isInConsecutiveRegs()) {
362 if (ArgFlags.isInConsecutiveRegs()) {
575 if (ArgFlags.isInConsecutiveRegs()) {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc268 if (ArgFlags.isInConsecutiveRegs()) {
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2743 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
2780 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
3420 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
5386 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5422 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5438 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3227 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
3264 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
3904 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
5947 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5983 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6001 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2557 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
3106 !Flags.isInConsecutiveRegs()) { in LowerCall()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp3060 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
3627 !Flags.isInConsecutiveRegs()) { in LowerCall()