| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 382 else if (ArgFlags.isZExt())
478 else if (ArgFlags.isZExt())
488 else if (ArgFlags.isZExt())
498 else if (ArgFlags.isZExt())
508 else if (ArgFlags.isZExt())
518 else if (ArgFlags.isZExt())
528 else if (ArgFlags.isZExt())
568 else if (ArgFlags.isZExt())
627 else if (ArgFlags.isZExt())
692 else if (ArgFlags.isZExt())
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineFrameInfo.h | 126 bool isZExt; member
135 PreAllocated(false), isAliased(A), isZExt(false), isSExt(false) {} in StackObject()
440 return Objects[ObjectIdx+NumFixedObjects].isZExt; in isObjectZExt()
446 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 164 bool isZExt);
166 unsigned Alignment = 0, bool isZExt = true,
175 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
920 unsigned Alignment, bool isZExt, bool allocReg) { in ARMEmitLoad() argument
932 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
934 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
936 if (isZExt) { in ARMEmitLoad()
951 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
953 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
955 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 195 bool isZExt, bool isEquality);
197 unsigned Alignment = 0, bool isZExt = true,
206 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
920 unsigned Alignment, bool isZExt, bool allocReg) { in ARMEmitLoad() argument
932 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
934 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
936 if (isZExt) { in ARMEmitLoad()
951 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
953 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
955 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineFrameInfo.h | 160 bool isZExt = false; member
477 return Objects[ObjectIdx+NumFixedObjects].isZExt; in isObjectZExt()
483 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
|
| D | TargetCallingConv.h | 63 bool isZExt() const { return IsZExt; } in isZExt() function
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenCallingConv.inc | 122 else if (ArgFlags.isZExt())
137 else if (ArgFlags.isZExt())
278 else if (ArgFlags.isZExt())
292 else if (ArgFlags.isZExt())
346 else if (ArgFlags.isZExt())
475 else if (ArgFlags.isZExt())
719 else if (ArgFlags.isZExt())
736 else if (ArgFlags.isZExt())
788 else if (ArgFlags.isZExt())
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCMachineFunctionInfo.cpp | 57 return LiveIn.second.isZExt(); in isLiveInZExt()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 127 else if (ArgFlags.isZExt())
301 else if (ArgFlags.isZExt())
361 else if (ArgFlags.isZExt())
400 else if (ArgFlags.isZExt())
429 else if (ArgFlags.isZExt())
491 else if (ArgFlags.isZExt())
530 else if (ArgFlags.isZExt())
627 else if (ArgFlags.isZExt())
675 else if (ArgFlags.isZExt())
|
| D | X86FastISel.cpp | 761 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
772 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetCallingConv.h | 50 bool isZExt() const { return Flags & ZExt; } in isZExt() function
|
| D | TargetLowering.h | 1212 bool isZExt : 1; member
1219 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 70 bool isZExt() const { return Flags & ZExt; } in isZExt() function
|
| D | TargetLowering.h | 2465 bool isZExt : 1; member
2476 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenCallingConv.inc | 126 else if (ArgFlags.isZExt())
325 else if (ArgFlags.isZExt())
467 else if (ArgFlags.isZExt())
643 else if (ArgFlags.isZExt())
765 else if (ArgFlags.isZExt())
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 139 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1504 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
1505 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
1553 bool isZExt = isa<ZExtInst>(I); in selectIntExt() local
1570 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1655 bool isZExt) { in emitIntExt() argument
1657 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 129 else if (ArgFlags.isZExt())
373 else if (ArgFlags.isZExt())
586 else if (ArgFlags.isZExt())
700 else if (ArgFlags.isZExt())
730 else if (ArgFlags.isZExt())
849 else if (ArgFlags.isZExt())
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 185 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1728 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
1729 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
1778 bool isZExt = isa<ZExtInst>(I); in selectIntExt() local
1795 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1881 bool isZExt) { in emitIntExt() argument
1883 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 17 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypes.cpp | 1050 Entry.isZExt = !isSigned; in MakeLibCall()
1081 Entry.isZExt = !isSigned; in ExpandChainLibCall()
|
| D | LegalizeDAG.cpp | 2206 Entry.isZExt = !isSigned; in ExpandLibCall()
2248 Entry.isZExt = !isSigned; in ExpandLibCall()
2286 Entry.isZExt = !isSigned; in ExpandChainLibCall()
2414 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2423 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 1949 Entry.isZExt = !isSigned; in ExpandLibCall()
2000 Entry.isZExt = !isSigned; in ExpandLibCall()
2034 Entry.isZExt = !isSigned; in ExpandChainLibCall()
2121 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2130 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2225 Entry.isZExt = false; in ExpandSinCosLibCall()
2233 Entry.isZExt = false; in ExpandSinCosLibCall()
2241 Entry.isZExt = false; in ExpandSinCosLibCall()
|
| D | LegalizeTypes.cpp | 1095 Entry.isZExt = !isSigned; in ExpandChainLibCall()
|