/external/llvm/test/CodeGen/Mips/msa/ |
D | spill.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1) 77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2) 78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3) 79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4) 80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5) 81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6) 82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7) 83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8) 84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9) [all …]
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D | elm_cxcmsa.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s 9 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0) 19 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1) 29 %0 = tail call i32 @llvm.mips.cfcmsa(i32 2) 39 %0 = tail call i32 @llvm.mips.cfcmsa(i32 3) 49 %0 = tail call i32 @llvm.mips.cfcmsa(i32 4) 59 %0 = tail call i32 @llvm.mips.cfcmsa(i32 5) 69 %0 = tail call i32 @llvm.mips.cfcmsa(i32 6) 79 %0 = tail call i32 @llvm.mips.cfcmsa(i32 7) 89 tail call void @llvm.mips.ctcmsa(i32 0, i32 1) [all …]
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D | bit.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7) 17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind 31 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7) 36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind 50 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7) 55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind 69 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7) 74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind 88 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7) [all …]
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D | i5-c.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 13 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14) 18 declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind 32 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14) 37 declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind 51 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14) 56 declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind 70 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14) 75 declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind 89 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14) [all …]
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D | i5-m.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 13 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14) 18 declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind 32 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14) 37 declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind 51 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14) 56 declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind 70 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14) 75 declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind 89 %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/ |
D | spill.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1) 77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2) 78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3) 79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4) 80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5) 81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6) 82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7) 83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8) 84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9) [all …]
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D | immediates-bad.ll | 1 ; RUN: not llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s 2> %t1 10 %r = call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %a, <16 x i8> %a, i32 65) 19 %r = call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %a, <16 x i8> %a, i32 5) 27 %r = call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %a, <16 x i8> %a, i32 63) 35 %r = call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %a, <16 x i8> %a, i32 63) 43 %r = call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %a, i32 6) 51 %r = call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %a, <16 x i8> %a, i32 63) 59 %r = call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %a, i32 9) 67 %r = call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %a, i32 152) 75 %r = call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %a, i32 163) [all …]
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D | immediates.ll | 1 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=… 16 %r = call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %a, i32 25) 26 %r = call <16 x i8> @llvm.mips.andi.b(<16 x i8> %a, i32 25) 36 %r = call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %a, i32 3) 47 %r = call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %a, <16 x i8> %b, i32 3) 58 %r = call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %a, <16 x i8> %b, i32 5) 69 %r = call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %a, <16 x i8> %b, i32 25) 80 %r = call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %a, <16 x i8> %b, i32 25) 90 %r = call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %a, i32 6) 100 %r = call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %a, <16 x i8> %a, i32 25) [all …]
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D | elm_cxcmsa.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s 9 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0) 19 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1) 29 %0 = tail call i32 @llvm.mips.cfcmsa(i32 2) 39 %0 = tail call i32 @llvm.mips.cfcmsa(i32 3) 49 %0 = tail call i32 @llvm.mips.cfcmsa(i32 4) 59 %0 = tail call i32 @llvm.mips.cfcmsa(i32 5) 69 %0 = tail call i32 @llvm.mips.cfcmsa(i32 6) 79 %0 = tail call i32 @llvm.mips.cfcmsa(i32 7) 89 tail call void @llvm.mips.ctcmsa(i32 0, i32 1) [all …]
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D | i5_ld_st.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 13 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16) 18 declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind 29 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 9) 43 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -512) 45 %2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 511) 61 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -513) 63 %2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 512) 84 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16) 89 declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind [all …]
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D | bit.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7) 17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind 31 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7) 36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind 50 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7) 55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind 69 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7) 74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind 88 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7) [all …]
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D | i5-c.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 13 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14) 18 declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind 32 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14) 37 declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind 51 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14) 56 declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind 70 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14) 75 declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind 89 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14) [all …]
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D | i5-m.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 13 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14) 18 declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind 32 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14) 37 declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind 51 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14) 56 declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind 70 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14) 75 declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind 89 %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
D | dsp-r1.ll | 8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15) 12 declare i32 @llvm.mips.extr.w(i64, i32) nounwind 18 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1) 26 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15) 30 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind 36 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1) 40 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind 46 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15) 50 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind 56 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1) [all …]
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D | dsp-r2.ll | 9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 13 declare i64 @llvm.mips.dpa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 25 declare i64 @llvm.mips.dps.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 37 declare i64 @llvm.mips.mulsa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 49 declare i64 @llvm.mips.dpax.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 61 declare i64 @llvm.mips.dpsx.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone [all …]
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D | brind-tailcall.ll | 1 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ 3 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ 5 ; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \ 7 ; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \ 9 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ 11 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ 13 ; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \ 15 ; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \ 17 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ 19 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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/external/llvm/test/CodeGen/Mips/ |
D | dsp-r1.ll | 8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15) 12 declare i32 @llvm.mips.extr.w(i64, i32) nounwind 18 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1) 26 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15) 30 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind 36 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1) 40 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind 46 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15) 50 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind 56 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1) [all …]
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D | dsp-r2.ll | 9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 13 declare i64 @llvm.mips.dpa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 25 declare i64 @llvm.mips.dps.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 37 declare i64 @llvm.mips.mulsa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 49 declare i64 @llvm.mips.dpax.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 61 declare i64 @llvm.mips.dpsx.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone [all …]
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/external/libvpx/libvpx/vpx_dsp/ |
D | vpx_dsp.mk | 14 DSP_SRCS-$(HAVE_MSA) += mips/macros_msa.h 67 DSP_SRCS-$(HAVE_MSA) += mips/add_noise_msa.c 68 DSP_SRCS-$(HAVE_MSA) += mips/deblock_msa.c 78 DSP_SRCS-$(HAVE_MSA) += mips/intrapred_msa.c 79 DSP_SRCS-$(HAVE_DSPR2) += mips/intrapred4_dspr2.c 80 DSP_SRCS-$(HAVE_DSPR2) += mips/intrapred8_dspr2.c 81 DSP_SRCS-$(HAVE_DSPR2) += mips/intrapred16_dspr2.c 83 DSP_SRCS-$(HAVE_DSPR2) += mips/common_dspr2.h 84 DSP_SRCS-$(HAVE_DSPR2) += mips/common_dspr2.c 141 DSP_SRCS-$(HAVE_MSA) += mips/vpx_convolve8_avg_horiz_msa.c [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
D | call.ll | 3 ; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck … 4 ; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck … 5 ; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck … 6 ; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck … 7 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tai… 8 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mip… 9 ; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck… 10 ; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck… 11 ; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck… 12 ; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck… [all …]
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/external/libunwind/ |
D | Android.bp | 58 mips: { 61 "include/tdep-mips", 67 "include/tdep-mips", 260 mips: { 262 "src/mips/is_fpreg.c", 263 "src/mips/regname.c", 264 "src/mips/Gcreate_addr_space.c", 265 "src/mips/Gget_proc_info.c", 266 "src/mips/Gget_save_loc.c", 267 "src/mips/Gglobal.c", [all …]
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/external/capstone/arch/Mips/ |
D | MipsInstPrinter.c | 96 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; in set_mem_access() 97 …MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INV… in set_mem_access() 98 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; in set_mem_access() 101 MI->flat_insn->detail->mips.op_count++; in set_mem_access() 198 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; in printOperand() 200 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; in printOperand() 201 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; in printOperand() 202 MI->flat_insn->detail->mips.op_count++; in printOperand() 222 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; in printOperand() 237 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; in printOperand() [all …]
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/external/llvm/test/CodeGen/Mips/llvm-ir/ |
D | call.ll | 3 ; FIXME: We should remove the need for -enable-mips-tail-calls 4 ; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -enable-mips-tail-calls < %s | FileCh… 5 ; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -enable-mips-tail-calls < %s | FileCh… 6 ; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -enable-mips-tail-calls < %s | FileCh… 7 ; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -enable-mips-tail-calls < %s | FileCh… 8 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -enable-mi… 9 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mip… 10 ; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes… 11 ; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes… 12 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes… [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | check-disabled-mcpus.ll | 2 ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ 4 ; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ 6 ; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ 9 ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ 12 ; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \ 15 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ 17 ; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \ 19 ; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \ 22 ; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ 24 ; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ [all …]
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/external/python/cpython2/Modules/_ctypes/ |
D | libffi.diff | 18 mips-sgi-irix5.* | mips-sgi-irix6.* | mips*-*-rtems*) 19 - TARGET=MIPS; TARGETDIR=mips 20 + TARGET=MIPS_IRIX; TARGETDIR=mips 22 mips*-*linux* | mips*-*-openbsd*) 25 - TARGET=MIPS; TARGETDIR=mips 26 + TARGET=MIPS_LINUX; TARGETDIR=mips 85 mips-sgi-irix5.* | mips-sgi-irix6.* | mips*-*-rtems*) 86 - TARGET=MIPS; TARGETDIR=mips 87 + TARGET=MIPS_IRIX; TARGETDIR=mips 89 mips*-*linux* | mips*-*-openbsd*) [all …]
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