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Searched refs:mtc1 (Results 1 – 25 of 189) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Dfmadd1.ll25 ; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
28 ; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
31 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
33 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
36 ; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
39 ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
43 ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
47 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
52 ; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
65 ; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
[all …]
Dfpxx.ll29 ; 32-NOFPXX: mtc1 $4, $f0
30 ; 32-NOFPXX: mtc1 $5, $f1
37 ; 32R2-NOFPXX: mtc1 $4, $f0
40 ; 32R2-FPXX: mtc1 $4, $f0
54 ; 32-NOFPXX: mtc1 $6, $f0
55 ; 32-NOFPXX: mtc1 $7, $f1
62 ; 32R2-NOFPXX: mtc1 $6, $f0
65 ; 32R2-FPXX: mtc1 $6, $f0
78 ; 32-NOFPXX: mtc1 $6, $f0
79 ; 32-NOFPXX: mtc1 $7, $f1
[all …]
Dselect.ll135 ; 32-DAG: mtc1 $5, $[[F0:f[0-9]+]]
136 ; 32-DAG: mtc1 $6, $[[F1:f0]]
139 ; 32R2-DAG: mtc1 $5, $[[F0:f[0-9]+]]
140 ; 32R2-DAG: mtc1 $6, $[[F1:f0]]
143 ; 32R6-DAG: mtc1 $5, $[[F0:f[0-9]+]]
144 ; 32R6-DAG: mtc1 $6, $[[F1:f[0-9]+]]
146 ; 32R6: mtc1 $[[T0]], $[[CC:f0]]
156 ; 64R6: mtc1 $[[T0]], $[[CC:f0]]
168 ; 32-DAG: mtc1 $6, $[[F0:f[1-3]*[02468]+]]
169 ; 32-DAG: mtc1 $7, $[[F0H:f[1-3]*[13579]+]]
[all …]
Dfp64a.ll3 ; use mfc1/mtc1 to move the bottom 32-bits (because the hardware will redirect
34 ; 32R2-NO-FP64A-LE: mtc1 $4, $f0
38 ; 32R2-NO-FP64A-BE: mtc1 $5, $f0
55 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
58 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
75 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
78 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
95 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
98 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
116 ; 32R2-NO-FP64A-LE-DAG: mtc1 $4, $[[T0:f[0-9]+]]
[all …]
Dmno-ldc1-sdc1.ll68 ; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0
69 ; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1
73 ; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0
78 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
85 ; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0
86 ; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1
92 ; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0
99 ; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0
104 ; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0
105 ; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1
[all …]
D2013-11-18-fp64-const0.ll13 ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[02468]}}
14 ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[13579]}}
16 ; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}}
17 ; CHECK-FP64-NOT: mtc1 $zero,
Dhf16call32.ll756 ; stel: mtc1 $4, $f12
769 ; stel: mtc1 $4, $f12
770 ; stel: mtc1 $5, $f13
779 ; stel: mtc1 $4, $f12
780 ; stel: mtc1 $5, $f14
789 ; stel: mtc1 $4, $f12
790 ; stel: mtc1 $6, $f14
791 ; stel: mtc1 $7, $f15
800 ; stel: mtc1 $4, $f12
801 ; stel: mtc1 $5, $f13
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dfpxx.ll29 ; 32-NOFPXX: mtc1 $4, $f0
30 ; 32-NOFPXX: mtc1 $5, $f1
37 ; 32R2-NOFPXX: mtc1 $4, $f0
40 ; 32R2-FPXX: mtc1 $4, $f0
54 ; 32-NOFPXX: mtc1 $6, $f0
55 ; 32-NOFPXX: mtc1 $7, $f1
62 ; 32R2-NOFPXX: mtc1 $6, $f0
65 ; 32R2-FPXX: mtc1 $6, $f0
78 ; 32-NOFPXX: mtc1 $6, $f0
79 ; 32-NOFPXX: mtc1 $7, $f1
[all …]
Dfmadd1.ll36 ; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
39 ; 32-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
42 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
44 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
47 ; 32R6-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
50 ; 32R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
54 ; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
58 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
63 ; 64R6-NOMADD-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
76 ; 32-NOMADD-DAG: mtc1 $6, $[[T0:f[0-9]+]]
[all …]
Dselect.ll181 ; 32-NEXT: mtc1 $6, $f0
182 ; 32-NEXT: mtc1 $5, $f1
188 ; 32R2-NEXT: mtc1 $6, $f0
189 ; 32R2-NEXT: mtc1 $5, $f1
197 ; 32R6-NEXT: mtc1 $5, $f1
198 ; 32R6-NEXT: mtc1 $6, $f2
199 ; 32R6-NEXT: mtc1 $1, $f0
219 ; 64R6-NEXT: mtc1 $1, $f0
231 ; 32-NEXT: mtc1 $6, $f2
232 ; 32-NEXT: mtc1 $7, $f3
[all …]
Dfp64a.ll3 ; use mfc1/mtc1 to move the bottom 32-bits (because the hardware will redirect
34 ; 32R2-NO-FP64A-LE: mtc1 $4, $f0
38 ; 32R2-NO-FP64A-BE: mtc1 $5, $f0
55 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
58 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
75 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
78 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
95 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
98 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
116 ; 32R2-NO-FP64A-LE-DAG: mtc1 $4, $[[T0:f[0-9]+]]
[all …]
Dmno-ldc1-sdc1.ll68 ; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0
69 ; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1
73 ; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0
78 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
85 ; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0
86 ; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1
92 ; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0
99 ; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0
104 ; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0
105 ; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1
[all …]
D2013-11-18-fp64-const0.ll13 ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[02468]}}
14 ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[13579]}}
16 ; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}}
17 ; CHECK-FP64-NOT: mtc1 $zero,
Danalyzebranch.ll13 ; MIPS32-NEXT: mtc1 $zero, $f2
14 ; MIPS32-NEXT: mtc1 $zero, $f3
19 ; MIPS32-NEXT: mtc1 $zero, $f0
20 ; MIPS32-NEXT: mtc1 $zero, $f1
34 ; MIPS32R2-NEXT: mtc1 $zero, $f2
40 ; MIPS32R2-NEXT: mtc1 $zero, $f0
55 ; MIPS32r6-NEXT: mtc1 $zero, $f1
62 ; MIPS32r6-NEXT: mtc1 $zero, $f0
171 ; MIPS32-NEXT: mtc1 $zero, $f0
189 ; MIPS32R2-NEXT: mtc1 $zero, $f0
[all …]
Dhf16call32.ll756 ; stel: mtc1 $4, $f12
769 ; stel: mtc1 $4, $f12
770 ; stel: mtc1 $5, $f13
779 ; stel: mtc1 $4, $f12
780 ; stel: mtc1 $5, $f14
789 ; stel: mtc1 $4, $f12
790 ; stel: mtc1 $6, $f14
791 ; stel: mtc1 $7, $f15
800 ; stel: mtc1 $4, $f12
801 ; stel: mtc1 $5, $f13
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
Dcallabi.ll283 ; ALL: mtc1 $[[REG_FPCONST]], $f12
298 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
301 ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14
316 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
332 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
349 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
371 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
372 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
390 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
391 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
[all …]
Dsimplestorefp1.ll21 ; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
37 ; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dcallabi.ll294 ; ALL: mtc1 $[[REG_FPCONST]], $f12
309 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
312 ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14
327 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
343 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
360 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
382 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
383 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
401 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
402 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
[all …]
Dsimplestorefp1.ll21 ; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
37 ; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-dbl.ll45 ; M2-NEXT: mtc1 $7, $f0
47 ; M2-NEXT: mtc1 $6, $f1
51 ; CMOV32R1-NEXT: mtc1 $7, $f2
52 ; CMOV32R1-NEXT: mtc1 $6, $f3
60 ; CMOV32R2-NEXT: mtc1 $7, $f2
69 ; 32R6-NEXT: mtc1 $7, $f1
71 ; 32R6-NEXT: mtc1 $4, $f0
96 ; 64R6-NEXT: mtc1 $4, $f0
102 ; MM32R3: mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
111 ; MM32R6-NEXT: mtc1 $7, $f1
[all …]
Dselect-flt.ll41 ; M2-NEXT: mtc1 $6, $f0
44 ; M2-NEXT: mtc1 $5, $f0
48 ; CMOV32R1-NEXT: mtc1 $6, $f0
50 ; CMOV32R1-NEXT: mtc1 $5, $f1
56 ; CMOV32R2-NEXT: mtc1 $6, $f0
58 ; CMOV32R2-NEXT: mtc1 $5, $f1
64 ; 32R6-NEXT: mtc1 $5, $f1
65 ; 32R6-NEXT: mtc1 $6, $f2
66 ; 32R6-NEXT: mtc1 $4, $f0
90 ; 64R6-NEXT: mtc1 $4, $f0
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dfcopysign.ll17 ; CHECK-EL: mtc1 $[[LO0]], $f0
18 ; CHECK-EL: mtc1 $[[OR]], $f1
30 ; CHECK-EB: mtc1 $[[OR]], $f0
31 ; CHECK-EB: mtc1 $[[LO0]], $f1
50 ; CHECK-EL: mtc1 $[[T4]], $f0
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll40 ; M2: mtc1 $6, $f0
44 ; M2: mtc1 $5, $f0
47 ; CMOV-32: mtc1 $6, $f0
48 ; CMOV-32: mtc1 $5, $f1
52 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
53 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
54 ; SEL-32: mtc1 $4, $f0
61 ; SEL-64: mtc1 $4, $f0
64 ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
65 ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
[all …]
Dselect-dbl.ll43 ; M2: mtc1 $7, $f0
45 ; M2: mtc1 $6, $f1
47 ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
48 ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
54 ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
57 ; SEL-32: mtc1 $4, $f0
72 ; SEL-64: mtc1 $4, $f0
75 ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]]
105 ; SEL-32: mtc1 $[[T0]], $f0
120 ; SEL-64: mtc1 $6, $f0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Df16-llvm-ir.ll55 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
84 ; MIPS32: mtc1 $[[R1]], $f[[F0:[0-9]+]]
129 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
139 ; MIPS32: mtc1 $[[R3]], $f[[F3:[0-9]+]]
151 ; MIPS32: mtc1 $[[R5]], $f[[F5:[0-9]+]]
177 ; MIPSR5: mtc1 $[[R16]], $f[[F7:[0-9]+]]
202 ; MIPS32: mtc1 $[[R2]], $f[[F0:[0-9]+]]
268 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
304 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
334 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
[all …]

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