| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | cik_sdma.c | 37 struct r600_resource *rdst = r600_resource(dst); in cik_sdma_copy_buffer() local
43 util_range_add(&rdst->valid_buffer_range, dst_offset, in cik_sdma_copy_buffer()
46 dst_offset += rdst->gpu_address; in cik_sdma_copy_buffer()
50 si_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc); in cik_sdma_copy_buffer()
78 struct r600_resource *rdst = r600_resource(dst); in cik_sdma_clear_buffer() local
89 util_range_add(&rdst->valid_buffer_range, offset, offset + size); in cik_sdma_clear_buffer()
91 offset += rdst->gpu_address; in cik_sdma_clear_buffer()
95 si_need_dma_space(&sctx->b, ncopy * 5, rdst, NULL); in cik_sdma_clear_buffer()
148 struct r600_texture *rdst = (struct r600_texture*)dst; in cik_sdma_copy_texture() local
149 unsigned bpp = rdst->surface.bpe; in cik_sdma_copy_texture()
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| D | si_dma.c | 38 struct r600_resource *rdst = (struct r600_resource*)dst; in si_dma_copy_buffer() local
44 util_range_add(&rdst->valid_buffer_range, dst_offset, in si_dma_copy_buffer()
47 dst_offset += rdst->gpu_address; in si_dma_copy_buffer()
62 si_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc); in si_dma_copy_buffer()
87 struct r600_resource *rdst = r600_resource(dst); in si_dma_clear_buffer() local
98 util_range_add(&rdst->valid_buffer_range, offset, offset + size); in si_dma_clear_buffer()
100 offset += rdst->gpu_address; in si_dma_clear_buffer()
104 si_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL); in si_dma_clear_buffer()
135 struct r600_texture *rdst = (struct r600_texture*)dst; in si_dma_copy_tile() local
136 unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode; in si_dma_copy_tile()
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| D | si_fence.c | 71 struct si_multi_fence **rdst = (struct si_multi_fence **)dst; in si_fence_reference() local
74 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) { in si_fence_reference()
75 ws->fence_reference(&(*rdst)->gfx, NULL); in si_fence_reference()
76 ws->fence_reference(&(*rdst)->sdma, NULL); in si_fence_reference()
77 tc_unflushed_batch_token_reference(&(*rdst)->tc_token, NULL); in si_fence_reference()
78 r600_resource_reference(&(*rdst)->fine.buf, NULL); in si_fence_reference()
79 FREE(*rdst); in si_fence_reference()
81 *rdst = rsrc; in si_fence_reference()
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| D | si_test_dma.c | 208 struct r600_texture *rdst; in si_test_dma() local
278 rdst = (struct r600_texture*)dst; in si_test_dma()
286 array_mode_to_string(sscreen, &rdst->surface), in si_test_dma()
295 si_clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true); in si_test_dma()
326 !rdst->surface.is_linear && in si_test_dma()
354 !rdst->surface.is_linear && in si_test_dma()
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| D | si_cp_dma.c | 212 struct r600_resource *rdst = r600_resource(dst); in si_clear_buffer() local
226 util_range_add(&rdst->valid_buffer_range, offset, in si_clear_buffer()
243 !ws->cs_is_buffer_referenced(sctx->b.gfx.cs, rdst->buf, in si_clear_buffer()
250 uint64_t va = rdst->gpu_address + offset; in si_clear_buffer()
274 rdst->TC_L2_dirty = true; in si_clear_buffer()
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| D | si_blit.c | 1205 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource; in si_blit() local
1217 if (rdst->surface.is_linear && in si_blit()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | evergreen_hw_context.c | 40 struct r600_resource *rdst = (struct r600_resource*)dst; in evergreen_dma_copy_buffer() local
46 util_range_add(&rdst->valid_buffer_range, dst_offset, in evergreen_dma_copy_buffer()
49 dst_offset += rdst->gpu_address; in evergreen_dma_copy_buffer()
63 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc); in evergreen_dma_copy_buffer()
69 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, in evergreen_dma_copy_buffer()
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| D | r600_buffer_common.c | 280 struct r600_resource *rdst = r600_resource(dst); in r600_replace_buffer_storage() local
282 uint64_t old_gpu_address = rdst->gpu_address; in r600_replace_buffer_storage()
284 pb_reference(&rdst->buf, rsrc->buf); in r600_replace_buffer_storage()
285 rdst->gpu_address = rsrc->gpu_address; in r600_replace_buffer_storage()
286 rdst->b.b.bind = rsrc->b.b.bind; in r600_replace_buffer_storage()
287 rdst->flags = rsrc->flags; in r600_replace_buffer_storage()
289 assert(rdst->vram_usage == rsrc->vram_usage); in r600_replace_buffer_storage()
290 assert(rdst->gart_usage == rsrc->gart_usage); in r600_replace_buffer_storage()
291 assert(rdst->bo_size == rsrc->bo_size); in r600_replace_buffer_storage()
292 assert(rdst->bo_alignment == rsrc->bo_alignment); in r600_replace_buffer_storage()
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| D | r600_test_dma.c | 208 struct r600_texture *rdst; in r600_test_dma() local
278 rdst = (struct r600_texture*)dst; in r600_test_dma()
286 array_mode_to_string(rscreen, &rdst->surface), in r600_test_dma()
295 rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true); in r600_test_dma()
326 !rdst->surface.is_linear && in r600_test_dma()
354 !rdst->surface.is_linear && in r600_test_dma()
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| D | r600_state.c | 2854 struct r600_texture *rdst = (struct r600_texture*)dst; in r600_dma_copy_tile() local
2859 dst_mode = rdst->surface.u.legacy.level[dst_level].mode; in r600_dma_copy_tile()
2883 addr = rdst->surface.u.legacy.level[dst_level].offset; in r600_dma_copy_tile()
2884 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; in r600_dma_copy_tile()
2889 …slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[ds… in r600_dma_copy_tile()
2896 height = u_minify(rdst->resource.b.b.height0, dst_level); in r600_dma_copy_tile()
2901 base = rdst->surface.u.legacy.level[dst_level].offset; in r600_dma_copy_tile()
2916 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource); in r600_dma_copy_tile()
2924 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE, in r600_dma_copy_tile()
2952 struct r600_texture *rdst = (struct r600_texture*)dst; in r600_dma_copy() local
[all …]
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| D | r600_hw_context.c | 577 struct r600_resource *rdst = (struct r600_resource*)dst; in r600_dma_copy_buffer() local
583 util_range_add(&rdst->valid_buffer_range, dst_offset, in r600_dma_copy_buffer()
589 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc); in r600_dma_copy_buffer()
595 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, in r600_dma_copy_buffer()
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| D | evergreen_state.c | 3696 struct r600_texture *rdst = (struct r600_texture*)dst; in evergreen_dma_copy_tile() local
3702 dst_mode = rdst->surface.u.legacy.level[dst_level].mode; in evergreen_dma_copy_tile()
3732 addr = rdst->surface.u.legacy.level[dst_level].offset; in evergreen_dma_copy_tile()
3733 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; in evergreen_dma_copy_tile()
3740 addr += rdst->resource.gpu_address; in evergreen_dma_copy_tile()
3744 …slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[ds… in evergreen_dma_copy_tile()
3751 height = u_minify(rdst->resource.b.b.height0, dst_level); in evergreen_dma_copy_tile()
3756 base = rdst->surface.u.legacy.level[dst_level].offset; in evergreen_dma_copy_tile()
3760 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh); in evergreen_dma_copy_tile()
3761 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw); in evergreen_dma_copy_tile()
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| D | r600_pipe_common.c | 1159 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst; in r600_fence_reference() local
1162 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) { in r600_fence_reference()
1163 ws->fence_reference(&(*rdst)->gfx, NULL); in r600_fence_reference()
1164 ws->fence_reference(&(*rdst)->sdma, NULL); in r600_fence_reference()
1165 FREE(*rdst); in r600_fence_reference()
1167 *rdst = rsrc; in r600_fence_reference()
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| D | r600_texture.c | 47 struct r600_texture *rdst, in r600_prepare_for_dma_blit() argument
57 if (rdst->surface.bpe != rsrc->surface.bpe) in r600_prepare_for_dma_blit()
62 rdst->resource.b.b.nr_samples > 1) in r600_prepare_for_dma_blit()
69 if (rsrc->is_depth || rdst->is_depth) in r600_prepare_for_dma_blit()
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) { in r600_prepare_for_dma_blit()
80 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level, in r600_prepare_for_dma_blit()
85 r600_texture_discard_cmask(rctx->screen, rdst); in r600_prepare_for_dma_blit()
93 assert(!(rdst->dirty_level_mask & (1 << dst_level))); in r600_prepare_for_dma_blit()
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| D | r600_blit.c | 622 struct r600_resource_global *rdst = in r600_copy_global_buffer() local
624 struct compute_memory_item *item = rdst->chunk; in r600_copy_global_buffer()
919 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource; in r600_blit() local
931 if (rdst->surface.u.legacy.level[info->dst.level].mode == in r600_blit()
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| D | r600_pipe_common.h | 747 struct r600_texture *rdst,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_buffer_common.c | 283 struct r600_resource *rdst = r600_resource(dst); in si_replace_buffer_storage() local
285 uint64_t old_gpu_address = rdst->gpu_address; in si_replace_buffer_storage()
287 pb_reference(&rdst->buf, rsrc->buf); in si_replace_buffer_storage()
288 rdst->gpu_address = rsrc->gpu_address; in si_replace_buffer_storage()
289 rdst->b.b.bind = rsrc->b.b.bind; in si_replace_buffer_storage()
290 rdst->b.max_forced_staging_uploads = rsrc->b.max_forced_staging_uploads; in si_replace_buffer_storage()
291 rdst->max_forced_staging_uploads = rsrc->max_forced_staging_uploads; in si_replace_buffer_storage()
292 rdst->flags = rsrc->flags; in si_replace_buffer_storage()
294 assert(rdst->vram_usage == rsrc->vram_usage); in si_replace_buffer_storage()
295 assert(rdst->gart_usage == rsrc->gart_usage); in si_replace_buffer_storage()
[all …]
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| D | r600_texture.c | 47 struct r600_texture *rdst, in si_prepare_for_dma_blit() argument
57 if (rdst->surface.bpe != rsrc->surface.bpe) in si_prepare_for_dma_blit()
62 rdst->resource.b.b.nr_samples > 1) in si_prepare_for_dma_blit()
69 if (rsrc->is_depth || rdst->is_depth) in si_prepare_for_dma_blit()
77 vi_dcc_enabled(rdst, dst_level)) in si_prepare_for_dma_blit()
85 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) { in si_prepare_for_dma_blit()
88 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level, in si_prepare_for_dma_blit()
93 r600_texture_discard_cmask(rctx->screen, rdst); in si_prepare_for_dma_blit()
101 assert(!(rdst->dirty_level_mask & (1 << dst_level))); in si_prepare_for_dma_blit()
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| D | r600_pipe_common.h | 589 struct r600_texture *rdst,
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_cs.h | 172 struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst; in amdgpu_fence_reference() local
175 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) { in amdgpu_fence_reference()
176 struct amdgpu_fence *fence = *rdst; in amdgpu_fence_reference()
186 *rdst = rsrc; in amdgpu_fence_reference()
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| /external/toybox/toys/pending/ |
| D | ip.c | 1447 struct I_data rvia, rdst, mdst, rsrc, msrc; member
1493 if (gfilter.rdst.family && (msg->rtm_family != gfilter.rdst.family || in display_route_info()
1494 gfilter.rdst.netmask > msg->rtm_dst_len)) return 0; in display_route_info()
1511 if (gfilter.rdst.family && in display_route_info()
1512 memcmp(RTA_DATA(attr[RTA_DST]), &gfilter.rdst.addr, gfilter.rdst.len)) in display_route_info()
1842 parse_prefix(gfilter.rdst.addr, &gfilter.rdst.netmask, in route_show_flush()
1843 &gfilter.rdst.len, *argv, gfilter.rdst.family); in route_show_flush()
1844 if (gfilter.rdst.len) in route_show_flush()
1845 gfilter.rdst.family = ((gfilter.rdst.len == 4) ? in route_show_flush()
1855 if (idx != 11) gfilter.rdst = gfilter.mdst; in route_show_flush()
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| /external/iproute2/ip/ |
| D | iproute.c | 130 inet_prefix rdst; member
192 if (filter.rdst.family && in filter_nlmsg()
193 (r->rtm_family != filter.rdst.family || filter.rdst.bitlen > r->rtm_dst_len)) in filter_nlmsg()
242 if (filter.rdst.family && inet_addr_match(&dst, &filter.rdst, filter.rdst.bitlen)) in filter_nlmsg()
1552 get_prefix(&filter.rdst, *argv, do_ipv6); in iproute_list_flush_or_save()
1561 filter.rdst = filter.mdst; in iproute_list_flush_or_save()
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| /external/mesa3d/src/gallium/state_trackers/nine/ |
| D | nine_shader.c | 1328 struct ureg_dst rdst; in tx_apply_dst0_modifiers() local
1333 rdst = _tx_dst_param(tx, &tx->insn.dst[0]); in tx_apply_dst0_modifiers()
1335 assert(rdst.File != TGSI_FILE_ADDRESS); /* this probably isn't possible */ in tx_apply_dst0_modifiers()
1342 ureg_MUL(tx->ureg, rdst, ureg_src(tx->regs.tdst), ureg_imm1f(tx->ureg, f)); in tx_apply_dst0_modifiers()
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| /external/cldr/tools/java/org/unicode/cldr/util/data/transforms/ |
| D | internal_raw_IPA.txt | 14436 beardstown %17661 bˈirdztaʊn, bˈɪrdstɑʊn
73232 hardstand %19285 hɑrdstˈænd, hˈɑrdstænd
179480 wordstar %25816 wˈərdstɑr
180318 yardstick %31238 jˈɑrdstɪk
180319 yardsticks %24964 jˈɑrdstɪks
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| D | internal_raw_IPA-old.txt | 16984 beardstown %2769 bˈirdztaʊn, bˈɪrdstǎn
86859 hardstand %8777 hɑrdstˈænd, hˈɑrdstænd
214878 wordstar %18434 wˈərdstɑr
216020 yardstick %22835 jˈɑrdstɪk
216021 yardsticks %14735 jˈɑrdstɪks
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