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Searched refs:readl (Results 1 – 25 of 923) sorted by relevance

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/external/u-boot/arch/arm/mach-uniphier/clk/
Dpll-ld4.c19 tmp = readl(SG_PINMON0); in upll_init()
24 tmp = readl(SC_UPLLCTRL); in upll_init()
59 tmp = readl(SG_PINMON0); in vpll_init()
63 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
66 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
71 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
74 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
79 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
82 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
87 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
[all …]
Dpll-pro4.c20 tmp = readl(SG_PINMON0); in vpll_init()
29 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
32 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
37 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
40 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
45 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
49 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
57 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
61 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
67 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
[all …]
/external/u-boot/arch/arm/cpu/pxa/
Dusb.c20 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); in usb_cpu_init()
25 writel(readl(CKEN) | CKEN10_USBHOST, CKEN); in usb_cpu_init()
33 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_init()
35 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); in usb_cpu_init()
37 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in usb_cpu_init()
38 while (readl(UHCHR) & UHCHR_FSBIR) in usb_cpu_init()
42 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); in usb_cpu_init()
45 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); in usb_cpu_init()
47 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); in usb_cpu_init()
54 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_stop()
[all …]
/external/u-boot/arch/arm/mach-exynos/
Dclock.c193 r = readl(&clk->apll_con0); in exynos4_get_pll_clk()
196 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
199 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
200 k = readl(&clk->epll_con1); in exynos4_get_pll_clk()
203 r = readl(&clk->vpll_con0); in exynos4_get_pll_clk()
204 k = readl(&clk->vpll_con1); in exynos4_get_pll_clk()
223 r = readl(&clk->apll_con0); in exynos4x12_get_pll_clk()
226 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
229 r = readl(&clk->epll_con0); in exynos4x12_get_pll_clk()
230 k = readl(&clk->epll_con1); in exynos4x12_get_pll_clk()
[all …]
/external/u-boot/arch/arm/cpu/arm926ejs/mx27/
Dgeneric.c48 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
59 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
67 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
73 ulong cscr = readl(&pll->cscr); in imx_get_armclk()
88 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk()
100 ulong cscr = readl(&pll->cscr); in imx_get_spllclk()
108 return imx_decode_pll(readl(&pll->spctl0), fref); in imx_get_spllclk()
120 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); in imx_get_perclk1()
127 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); in imx_get_perclk2()
134 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); in imx_get_perclk3()
[all …]
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dclock_ti816x.c141 while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) in enable_dmm_clocks()
153 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) in enable_emif_clocks()
156 while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
159 while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
175 readl(CONTROL_STATUS); in ddr_delay()
183 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
189 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
195 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
229 while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) in main_pll_init_ti816x()
233 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
[all …]
/external/u-boot/arch/arm/mach-imx/mx7ulp/
Dscg.c22 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
28 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
34 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
40 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
74 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
78 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
112 reg = readl(&scg1_regs->firccsr); in scg_fircdiv_get_rate()
116 reg = readl(&scg1_regs->fircdiv); in scg_fircdiv_get_rate()
150 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
154 reg = readl(&scg1_regs->soscdiv); in scg_soscdiv_get_rate()
[all …]
/external/u-boot/drivers/usb/gadget/
Ddesignware_udc.c145 writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, in udc_stall_ep()
148 writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, in udc_stall_ep()
158 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); in get_fifo()
162 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); in get_fifo()
169 readl(&outep_regs_p[2].endp_maxpacksize) >> 16; in get_fifo()
176 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; in get_fifo()
191 if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) in usbgetpckfromfifo()
204 writel(readl(fifo_ptr), wrdp); in usbgetpckfromfifo()
214 readl(&outep_regs_p[epNum].write_done); in usbgetpckfromfifo()
383 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; in dw_udc_ep0_rx()
[all …]
Dpxa27x_udc.c40 writel(readl(USIR1) | mask, USIR1); in udc_ack_int_UDCCR()
101 while (!(readl(UDCCSN(ep_num)) & UDCCSR_PC)) { in udc_write_urb()
150 if (readl(UDCCSN(ep_num)) & UDCCSR_BNE) in udc_read_urb()
151 n = readl(UDCBCN(ep_num)) & 0x3ff; in udc_read_urb()
157 data32[urb->actual_length / 4 + i / 4] = readl(UDCDN(ep_num)); in udc_read_urb()
177 n = readl(UDCBCR0); in udc_read_urb_ep0()
182 data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0)); in udc_read_urb_ep0()
204 u32 udccsr0 = readl(UDCCSR0); in udc_handle_ep0()
224 udccsr0 = readl(UDCCSR0); in udc_handle_ep0()
234 if ((readl(UDCCSR0) & UDCCSR0_RNE) == 0) { in udc_handle_ep0()
[all …]
Ddwc2_udc_otg_phy.c52 writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); in otg_phy_init()
55 writel((readl(&phy->phypwr) in otg_phy_init()
59 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) in otg_phy_init()
63 writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | in otg_phy_init()
67 writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | in otg_phy_init()
70 writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) in otg_phy_init()
73 writel(readl(&phy->rstcon) in otg_phy_init()
87 writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); in otg_phy_off()
90 writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN in otg_phy_off()
93 writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); in otg_phy_off()
[all …]
/external/u-boot/arch/arm/mach-omap2/omap5/
Dhwinit.c104 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) in io_settings_ddr3()
109 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) in io_settings_ddr3()
130 io_settings = readl((*ctrl)->control_smart1io_padconf_0) & in do_io_settings()
138 io_settings = readl((*ctrl)->control_smart1io_padconf_1) & in do_io_settings()
145 io_settings = readl((*ctrl)->control_smart1io_padconf_2) & in do_io_settings()
152 io_settings = readl((*ctrl)->control_smart2io_padconf_0) & in do_io_settings()
159 io_settings = readl((*ctrl)->control_smart2io_padconf_1) & in do_io_settings()
166 io_settings = readl((*ctrl)->control_smart2io_padconf_2) & in do_io_settings()
174 io_settings = readl((*ctrl)->control_smart3io_padconf_1) & in do_io_settings()
210 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
[all …]
/external/u-boot/drivers/video/exynos/
Dexynos_mipi_dsi_lowlevel.c25 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
39 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release()
63 unsigned int reg = readl(&mipi_dsim->intmsk); in exynos_mipi_dsi_set_interrupt_mask()
80 reg = readl(&mipi_dsim->fifoctrl); in exynos_mipi_dsi_init_fifo_pointer()
109 reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY); in exynos_mipi_dsi_set_main_disp_resol()
127 reg = (readl(&mipi_dsim->mvporch)) & in exynos_mipi_dsi_set_main_disp_vporch()
145 reg = (readl(&mipi_dsim->mhporch)) & in exynos_mipi_dsi_set_main_disp_hporch()
160 reg = (readl(&mipi_dsim->msync)) & in exynos_mipi_dsi_set_main_disp_sync_area()
176 reg = (readl(&mipi_dsim->sdresol)) & in exynos_mipi_dsi_set_sub_disp_resol()
[all …]
/external/u-boot/board/toradex/colibri_pxa270/
Dcolibri_pxa270.c65 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & in board_usb_init()
69 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in board_usb_init()
74 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); in board_usb_init()
78 if (readl(PSSR) & PSSR_OTGPH) in board_usb_init()
79 writel(readl(PSSR) | PSSR_OTGPH, PSSR); in board_usb_init()
81 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); in board_usb_init()
82 writel(readl(UHCRHDA) | 0x100, UHCRHDA); in board_usb_init()
85 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); in board_usb_init()
88 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | in board_usb_init()
101 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_board_stop()
[all …]
/external/u-boot/arch/arm/cpu/armv7/stv0991/
Dpinmux.c20 writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | in stv0991_pinmux_config()
23 writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | in stv0991_pinmux_config()
27 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | in stv0991_pinmux_config()
30 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | in stv0991_pinmux_config()
36 writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | in stv0991_pinmux_config()
39 writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | in stv0991_pinmux_config()
44 writel(readl(&stv0991_creg->mux6) & 0x000000FF, in stv0991_pinmux_config()
48 writel(readl(&stv0991_creg->mux9) & 0xFFF00000, in stv0991_pinmux_config()
51 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
53 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
[all …]
/external/u-boot/drivers/net/pfe_eth/
Dpfe_cmd.c178 val = readl(TMU_TEQ_DROP_STAT); in qm_read_drop_stat()
201 drops, readl(TMU_TEQ_TRANS_STAT), in tmu_queue_stats()
202 readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR), in tmu_queue_stats()
203 readl(TMU_LLM_QUE_DROPCNT)); in tmu_queue_stats()
223 printf(" tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR)); in hif_status()
224 printf(" tx status: %x\n", readl(HIF_TX_STATUS)); in hif_status()
225 printf(" tx dma status: %x\n", readl(HIF_TX_DMA_STATUS)); in hif_status()
227 printf(" rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR)); in hif_status()
228 printf(" rx status: %x\n", readl(HIF_RX_STATUS)); in hif_status()
229 printf(" rx dma status: %x\n", readl(HIF_RX_DMA_STATUS)); in hif_status()
[all …]
/external/u-boot/arch/arm/cpu/arm926ejs/mxs/
Dspl_power_init.c90 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) in mxs_power_set_auto_restart()
94 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) in mxs_power_set_auto_restart()
98 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) in mxs_power_set_auto_restart()
101 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) in mxs_power_set_auto_restart()
108 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) in mxs_power_set_auto_restart()
110 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) in mxs_power_set_auto_restart()
153 uint32_t volt = readl(&power_regs->hw_power_battmonitor); in mxs_get_batt_volt()
367 if (xfer && (readl(&power_regs->hw_power_5vctrl) & in mxs_enable_4p2_dcdc_input()
372 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & in mxs_enable_4p2_dcdc_input()
374 prev_5v_droop = readl(&power_regs->hw_power_ctrl) & in mxs_enable_4p2_dcdc_input()
[all …]
/external/u-boot/cmd/
Darmflash.c50 val = readl((void *)start + i); in compute_crc()
90 foot1 = readl((void *)secend - 0x0c); in parse_bank()
97 afi->flash_mem_start = readl((void *)secend - 0x10); in parse_bank()
98 afi->flash_mem_end = readl((void *)secend - 0x14); in parse_bank()
99 afi->attributes = readl((void *)secend - 0x08); in parse_bank()
104 afi->regions[0].offset = readl((void *)imginfo + 0x04); in parse_bank()
106 readl((void *)imginfo + 0x08); in parse_bank()
107 afi->regions[0].size = readl((void *)imginfo + 0x0C); in parse_bank()
108 afi->entrypoint = readl((void *)imginfo + 0x10); in parse_bank()
114 foot1 = readl((void *)secend - 0x04); in parse_bank()
[all …]
/external/u-boot/arch/arm/mach-at91/arm926ejs/
Deflash.c73 if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { in flash_init()
80 while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) in flash_init()
82 id = readl(&eefc->frr); /* word 0 */ in flash_init()
83 size = readl(&eefc->frr); /* word 1 */ in flash_init()
84 pagesize = readl(&eefc->frr); /* word 2 */ in flash_init()
85 nplanes = readl(&eefc->frr); /* word 3 */ in flash_init()
86 planesize = readl(&eefc->frr); /* word 4 */ in flash_init()
90 tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */ in flash_init()
92 nlocks = readl(&eefc->frr); /* word 4+nplanes */ in flash_init()
107 tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ in flash_init()
[all …]
/external/u-boot/arch/arm/cpu/arm1136/mx35/
Dgeneric.c57 reg = readl(&iim->iim_srev); in get_cpu_rev()
135 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); in get_mcu_main_clk()
136 fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); in get_mcu_main_clk()
145 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_clk()
155 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_per_clk()
156 u32 pdr4 = readl(&ccm->pdr4); in get_ipg_per_clk()
176 u32 pdr4 = readl(&ccm->pdr4); in imx_get_uartclk()
178 if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) in imx_get_uartclk()
181 freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); in imx_get_uartclk()
195 u32 reg = readl(&ccm->pdr0); in mxc_get_main_clock()
[all …]
/external/u-boot/arch/arm/cpu/arm926ejs/spear/
Dspear600.c34 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in sel_1v8()
39 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in sel_1v8()
44 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) in sel_1v8()
53 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in sel_2v5()
58 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in sel_2v5()
63 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) in sel_2v5()
77 ddrpad = readl(&misc_p->ddr_pad); in plat_ddr_init()
90 core3v3 = readl(&misc_p->core_3v3_compensation); in plat_ddr_init()
95 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in plat_ddr_init()
100 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in plat_ddr_init()
[all …]
/external/u-boot/drivers/net/
Dbcm-sf2-eth-gmac.c62 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()
64 if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) { in dma_ctrlflags()
81 uint32_t v = readl(reg); in reg32_clear_bits()
88 uint32_t v = readl(reg); in reg32_set_bits()
102 readl(GMAC0_DMA_TX_CTRL_ADDR), in dma_tx_dump()
103 readl(GMAC0_DMA_TX_PTR_ADDR), in dma_tx_dump()
104 readl(GMAC0_DMA_TX_ADDR_LOW_ADDR), in dma_tx_dump()
105 readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR), in dma_tx_dump()
106 readl(GMAC0_DMA_TX_STATUS0_ADDR), in dma_tx_dump()
107 readl(GMAC0_DMA_TX_STATUS1_ADDR)); in dma_tx_dump()
[all …]
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dwarmboot_avp.c50 if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP) in wb_start()
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
61 osc_ctrl.word = readl(&clkrst->crc_osc_ctrl); in wb_start()
67 if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { in wb_start()
70 while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
83 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); in wb_start()
99 reg = readl(&pmc->pmc_scratch41); in wb_start()
111 reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]); in wb_start()
116 reg = readl(TIMER_USEC_CNTR); in wb_start()
[all …]
/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_gen5.c82 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
127 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
128 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
234 u32 mainvco = readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
240 u32 periphvco = readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
296 cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); in cm_basic_init()
323 reg = readl(&clock_manager_base->main_pll.vco); in cm_get_main_vco_clk_hz()
338 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
349 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
[all …]
/external/u-boot/drivers/mtd/nand/
Darasan_nfc.c270 reg_val = readl(&arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
331 reg_val = readl(&arasan_nand_base->intsts_enr); in arasan_nand_read_page()
336 reg_val = readl(&arasan_nand_base->pkt_reg); in arasan_nand_read_page()
358 while (!(readl(&arasan_nand_base->intsts_reg) & in arasan_nand_read_page()
371 reg_val = readl(&arasan_nand_base->intsts_enr); in arasan_nand_read_page()
375 reg_val = readl(&arasan_nand_base->intsts_enr); in arasan_nand_read_page()
379 reg_val = readl(&arasan_nand_base->intsts_reg); in arasan_nand_read_page()
384 bufptr[i] = readl(&arasan_nand_base->buf_dataport); in arasan_nand_read_page()
398 while (!(readl(&arasan_nand_base->intsts_reg) & in arasan_nand_read_page()
408 reg_val = readl(&arasan_nand_base->intsts_enr); in arasan_nand_read_page()
[all …]
/external/u-boot/board/hisilicon/hikey/
Dhikey.c153 data = readl(clk_base); in hi6220_clk_enable()
158 data = readl(clk_base + STAT_EN_OFF); in hi6220_clk_enable()
169 data = readl(clk_base); in hi6220_clk_disable()
174 data = readl(clk_base + STAT_DIS_OFF); in hi6220_clk_disable()
192 data = readl(&peri_sc->rst0_stat); in board_usb_init()
198 data = readl(&peri_sc->ctrl5); in board_usb_init()
207 data = readl(&peri_sc->ctrl4); in board_usb_init()
251 data = readl(&peri_sc->clk0_sel); in mmc1_init_pll()
257 data = readl(&peri_sc->clk0_sel); in mmc1_init_pll()
267 data = readl(&peri_sc->clkcfg8bit2); in mmc1_init_pll()
[all …]

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