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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td214 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm),
215 OpcodeStr, "$rd, ${imm}(${rs1})">;
220 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm),
221 OpcodeStr, "$rs2, ${imm}(${rs1})">;
226 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
227 OpcodeStr, "$rd, ${imm}(${rs1})">;
232 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
233 OpcodeStr, "$rs2, ${imm}(${rs1})">;
238 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
239 OpcodeStr, "$rs1, $imm"> {
[all …]
DRISCVInstrInfoF.td40 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
41 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
44 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
45 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
50 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
55 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr,
56 "$rd, $rs1, $rs2, $funct3">;
59 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
60 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
65 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
[all …]
DRISCVInstrInfoD.td36 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
37 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
40 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
41 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
46 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
51 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
52 "$rd, $rs1, $rs2, $funct3">;
55 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
56 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
61 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
[all …]
DRISCVInstrInfo.td220 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
221 opcodestr, "$rs1, $rs2, $imm12"> {
228 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
229 opcodestr, "$rd, ${imm12}(${rs1})">;
237 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
238 opcodestr, "$rs2, ${imm12}(${rs1})">;
242 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
243 opcodestr, "$rd, $rs1, $imm12">;
248 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
249 "$rd, $rs1, $shamt">;
[all …]
DRISCVInstrFormats.td119 bits<5> rs1;
124 let Inst{19-15} = rs1;
135 bits<5> rs1;
142 let Inst{19-15} = rs1;
153 bits<5> rs1;
160 let Inst{19-15} = rs1;
170 bits<5> rs1;
176 let Inst{19-15} = rs1;
186 bits<5> rs1;
190 let Inst{19-15} = rs1;
[all …]
DRISCVInstrFormatsC.td40 bits<5> rs1;
44 let Inst{11-7} = rs1;
57 bits<5> rs1;
73 bits<5> rs1;
98 bits<3> rs1;
101 let Inst{9-7} = rs1;
113 bits<3> rs1;
116 let Inst{9-7} = rs1;
125 bits<3> rs1;
128 let Inst{9-7} = rs1;
DRISCVInstrInfoA.td22 (outs GPR:$rd), (ins GPR:$rs1),
23 opcodestr, "$rd, (${rs1})"> {
37 (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
38 opcodestr, "$rd, $rs2, (${rs1})">;
/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
31 let rd = 0, rs1 = 0, rs2 = 0 in
35 // For VIS Instructions with only rs1, rd operands.
39 (outs RC:$rd), (ins RC:$rs1),
40 !strconcat(OpcStr, " $rs1, $rd"), []>;
43 let rs1 = 0 in
50 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
[all …]
DSparcInstrInfo.td292 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
293 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
294 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
297 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
298 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
299 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
307 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
308 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
[all …]
DSparcInstrAliases.td143 // t<cond> %icc, rs1 + rs2
144 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
145 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
153 // t<cond> %xcc, rs1 + rs2
154 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
155 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
164 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
165 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
166 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
173 // t<cond> %icc, rs1 + imm
[all …]
DSparcInstr64Bit.td167 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
168 "add $rs1, $rs2, $rd, $sym",
170 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
193 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
194 "mulx $rs1, $rs2, $rd",
195 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
198 "mulx $rs1, $simm13, $rd",
199 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
204 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
[all …]
DSparcInstrFormats.td91 bits<5> rs1;
101 let Inst{18-14} = rs1;
115 bits<5> rs1;
119 let Inst{18-14} = rs1;
177 let rs1 = 0;
230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
231 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
232 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
234 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
235 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrVIS.td21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
31 let rd = 0, rs1 = 0, rs2 = 0 in
35 // For VIS Instructions with only rs1, rd operands.
39 (outs RC:$rd), (ins RC:$rs1),
40 !strconcat(OpcStr, " $rs1, $rd"), []>;
43 let rs1 = 0 in
50 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
[all …]
DSparcInstrInfo.td296 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
297 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
298 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
301 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
302 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
303 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
312 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
315 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
316 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
[all …]
DSparcInstrAliases.td143 // t<cond> %icc, rs1 + rs2
144 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
145 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
153 // t<cond> %xcc, rs1 + rs2
154 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
155 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
164 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
165 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
166 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
173 // t<cond> %icc, rs1 + imm
[all …]
DSparcInstr64Bit.td167 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
168 "add $rs1, $rs2, $rd, $sym",
170 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
193 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
194 "mulx $rs1, $rs2, $rd",
195 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
198 "mulx $rs1, $simm13, $rd",
199 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
204 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
[all …]
DSparcInstrFormats.td91 bits<5> rs1;
101 let Inst{18-14} = rs1;
115 bits<5> rs1;
119 let Inst{18-14} = rs1;
177 let rs1 = 0;
230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
231 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
232 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
234 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
235 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
[all …]
/external/u-boot/post/lib_powerpc/
Dcpu_asm.h142 #define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ argument
144 ((rs1) << 16) + \
150 #define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ argument
151 ((rs1) << 21) + \
154 #define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ argument
156 ((rs1) << 16) + \
162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument
164 ((rs1) << 21) + \
202 #define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) argument
204 #define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) argument
/external/eigen/test/
Dschur_real.cpp61 RealSchur<MatrixType> rs1; in schur() local
62 rs1.compute(A); in schur()
64 VERIFY_IS_EQUAL(rs1.info(), Success); in schur()
66 VERIFY_IS_EQUAL(rs1.matrixT(), rs2.matrixT()); in schur()
67 VERIFY_IS_EQUAL(rs1.matrixU(), rs2.matrixU()); in schur()
73 VERIFY_IS_EQUAL(rs3.matrixT(), rs1.matrixT()); in schur()
74 VERIFY_IS_EQUAL(rs3.matrixU(), rs1.matrixU()); in schur()
91 VERIFY_IS_EQUAL(rs1.matrixT(), rsOnlyT.matrixT()); in schur()
/external/javasqlite/src/main/java/SQLite/JDBC2z/
DJDBCDatabaseMetaData.java732 JDBCResultSet rs1 = null; in getBestRowIdentifier() local
742 rs1 = (JDBCResultSet) in getBestRowIdentifier()
766 rs1 != null && rs1.tr != null && rs1.tr.nrows > 0) { in getBestRowIdentifier()
772 for (int i = 0; i < rs1.tr.ncolumns; i++) { in getBestRowIdentifier()
773 h1.put(rs1.tr.column[i], Integer.valueOf(i)); // android-changed in getBestRowIdentifier()
806 for (int m = 0; m < rs1.tr.nrows; m++) { in getBestRowIdentifier()
807 String r1[] = (String [])(rs1.tr.rows.elementAt(m)); in getBestRowIdentifier()
904 JDBCResultSet rs1 = null; in getPrimaryKeys() local
906 rs1 = (JDBCResultSet) in getPrimaryKeys()
913 if (rs1 == null || rs1.tr == null || rs1.tr.nrows <= 0) { in getPrimaryKeys()
[all …]
/external/capstone/arch/Sparc/
DSparcDisassembler.c257 unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); in DecodeMem() local
274 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeMem()
378 unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); in DecodeJMPL() local
394 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeJMPL()
414 unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); in DecodeReturn() local
424 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeReturn()
445 unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); in DecodeSWAP() local
461 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeSWAP()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp384 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeMem() local
403 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeMem()
541 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeJMPL() local
556 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeJMPL()
574 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeReturn() local
584 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeReturn()
603 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeSWAP() local
620 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeSWAP()
642 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeTRAP() local
653 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeTRAP()
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp382 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeMem() local
401 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeMem()
539 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeJMPL() local
554 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeJMPL()
572 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeReturn() local
582 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeReturn()
601 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeSWAP() local
618 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeSWAP()
640 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeTRAP() local
651 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); in DecodeTRAP()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dswp-order-copies.ll23 %1 = tail call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %0, i64 %v2)
34 declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) #1
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrFormats.td69 bits<5> rs1;
73 let Inst{18-14} = rs1;

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