| /external/llvm/test/CodeGen/SystemZ/ |
| D | fp-sub-01.ll | 19 ; CHECK: seb %f0, 0(%r2)
29 ; CHECK: seb %f0, 4092(%r2)
42 ; CHECK: seb %f0, 0(%r2)
54 ; CHECK: seb %f0, 0(%r2)
66 ; CHECK: seb %f0, 400(%r1,%r2)
79 ; CHECK: seb %f0, 16{{[04]}}(%r15)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | fp-sub-01.ll | 21 ; CHECK: seb %f0, 0(%r2)
31 ; CHECK: seb %f0, 4092(%r2)
44 ; CHECK: seb %f0, 0(%r2)
56 ; CHECK: seb %f0, 0(%r2)
68 ; CHECK: seb %f0, 400(%r1,%r2)
81 ; CHECK-SCALAR: seb %f0, 16{{[04]}}(%r15)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | callabi.ll | 18 ; 32R2: seb $4, $[[T0]]
63 ; 32R2-DAG: seb $4, $[[T0]]
64 ; 32R2-DAG: seb $5, $[[T1]]
117 ; 32R2-DAG: seb $4, $[[T0]]
118 ; 32R2-DAG: seb $5, $[[T1]]
119 ; 32R2-DAG: seb $6, $[[T2]]
169 ; 32R2: seb $4, $[[R]]
173 ; 32R2: seb $5, $[[R]]
177 ; 32R2: seb $6, $[[R]]
181 ; 32R2: seb $7, $[[R]]
[all …]
|
| D | sel1.ll | 20 ; FIXME: The seb $X, $zero and xor .., .., $x instructions are redundant.
24 ; CHECK-NEXT: seb $1, $4
25 ; CHECK-NEXT: seb $2, $zero
|
| D | loadstoreconv.ll | 81 ; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
171 ; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | callabi.ll | 18 ; 32R2: seb $4, $[[T0]]
63 ; 32R2-DAG: seb $4, $[[T0]]
64 ; 32R2-DAG: seb $5, $[[T1]]
117 ; 32R2-DAG: seb $4, $[[T0]]
118 ; 32R2-DAG: seb $5, $[[T1]]
119 ; 32R2-DAG: seb $6, $[[T2]]
185 ; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]]
188 ; 32R2-DAG: seb $5, $[[T1]]
189 ; 32R2-DAG: seb $6, $[[T2]]
191 ; 32R2: seb $7, $[[T5]]
[all …]
|
| D | sel1.ll | 23 ; CHECK-DAG: seb $[[T0:[0-9]+]], $4
25 ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero
|
| D | loadstoreconv.ll | 81 ; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
171 ; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | add.ll | 63 ; R2-R6: seb $2, $[[T0:[0-9]+]]
66 ; MMR6: seb $2, $[[T0]]
195 ; R2-R6: seb $2, $[[T0]]
198 ; MM32: seb $2, $[[T0]]
201 ; MM64: seb $2, $[[T0]]
332 ; R2-R6: seb $2, $[[T0]]
335 ; MMR6: seb $2, $[[T0]]
|
| D | mul.ll | 84 ; 32R2-R5: seb $2, $[[T0]]
87 ; 32R6: seb $2, $[[T0]]
99 ; 64R2: seb $2, $[[T0]]
102 ; 64R6: seb $2, $[[T0]]
105 ; MM32: seb $2, $[[T0]]
|
| D | srem.ll | 79 ; R2-R5: seb $2, $[[T0]]
83 ; R6: seb $2, $[[T0]]
88 ; MMR3: seb $2, $[[T0]]
92 ; MMR6: seb $2, $[[T0]]
|
| D | sdiv.ll | 83 ; R2-R5: seb $2, $[[T0]]
88 ; R6: seb $2, $[[T0]]
93 ; MMR3: seb $2, $[[T0]]
97 ; MMR6: seb $2, $[[T0]]
|
| D | urem.ll | 91 ; R2-R5: seb $2, $[[T2]]
97 ; R6: seb $2, $[[T2]]
104 ; MMR3: seb $2, $[[T2]]
110 ; MMR6: seb $2, $[[T2]]
|
| D | sub.ll | 59 ; R2-R6: seb $2, $[[T0:[0-9]+]]
62 ; MM: seb $[[T0]], $[[T0]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | mul.ll | 83 ; 32R2-R5: seb $2, $[[T0]]
86 ; 32R6: seb $2, $[[T0]]
98 ; 64R2: seb $2, $[[T0]]
101 ; 64R6: seb $2, $[[T0]]
104 ; MM32: seb $2, $[[T0]]
|
| D | srem.ll | 79 ; R2-R5: seb $2, $[[T0]]
83 ; R6: seb $2, $[[T0]]
88 ; MMR3: seb $2, $[[T0]]
92 ; MMR6: seb $2, $[[T0]]
|
| D | sdiv.ll | 83 ; R2-R5: seb $2, $[[T0]]
88 ; R6: seb $2, $[[T0]]
93 ; MMR3: seb $2, $[[T0]]
97 ; MMR6: seb $2, $[[T0]]
|
| D | urem.ll | 89 ; R2-R5: seb $2, $[[T2]]
95 ; R6: seb $2, $[[T2]]
102 ; MMR3: seb $2, $[[T2]]
108 ; MMR6: seb $2, $[[T2]]
|
| D | add.ll | 67 ; R2-R6: seb $2, $[[T0:[0-9]+]]
70 ; MMR6: seb $2, $[[T0]]
249 ; R2-R6: seb $2, $[[T0]]
252 ; MM32: seb $2, $[[T0]]
397 ; R2-R6: seb $2, $[[T0]]
400 ; MMR6: seb $2, $[[T0]]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | 2008-07-16-SignExtInReg.ll | 7 ; CHECK: seb
|
| D | atomic.ll | 165 ; HAS-SEB-SEH: seb $2, $[[R18]]
210 ; HAS-SEB-SEH:seb $2, $[[R18]]
256 ; HAS-SEB-SEH: seb $2, $[[R19]]
296 ; HAS-SEB-SEH: seb $2, $[[R16]]
345 ; HAS-SEB-SEH: seb $2, $[[R17]]
393 ; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | 2008-07-16-SignExtInReg.ll | 7 ; CHECK: seb
|
| D | atomic.ll | 2394 ; MIPS32R2-NEXT: seb $1, $1
2397 ; MIPS32R2-NEXT: seb $2, $1
2425 ; MIPS32R6-NEXT: seb $1, $1
2428 ; MIPS32R6-NEXT: seb $2, $1
2458 ; MIPS32R6O0-NEXT: seb $6, $6
2464 ; MIPS32R6O0-NEXT: seb $2, $1
2563 ; MIPS64R2-NEXT: seb $1, $1
2566 ; MIPS64R2-NEXT: seb $2, $1
2594 ; MIPS64R6-NEXT: seb $1, $1
2597 ; MIPS64R6-NEXT: seb $2, $1
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | 2008-07-16-SignExtInReg.ll | 3 ; DISABLED: grep seb %t | count 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 246 … seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
248 … seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
|