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Searched refs:setgt (Results 1 – 25 of 49) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Ddagcombine-and-setcc.ll10 ; (and (setgt X, true), (setgt Y, true)) -> (setgt (or X, Y), true)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Ddagcombine-and-setcc.ll10 ; (and (setgt X, true), (setgt Y, true)) -> (setgt (or X, Y), true)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPatternsHVX.td461 def: OpR_RR_pat<V6_vgtb, setgt, VecQ8, HVI8>;
462 def: OpR_RR_pat<V6_vgth, setgt, VecQ16, HVI16>;
463 def: OpR_RR_pat<V6_vgtw, setgt, VecQ32, HVI32>;
478 def: AccRRR_pat<V6_vgtb_and, And, setgt, HQ8, HVI8, HVI8>;
479 def: AccRRR_pat<V6_vgtb_or, Or, setgt, HQ8, HVI8, HVI8>;
480 def: AccRRR_pat<V6_vgtb_xor, Xor, setgt, HQ8, HVI8, HVI8>;
481 def: AccRRR_pat<V6_vgth_and, And, setgt, HQ16, HVI16, HVI16>;
482 def: AccRRR_pat<V6_vgth_or, Or, setgt, HQ16, HVI16, HVI16>;
483 def: AccRRR_pat<V6_vgth_xor, Xor, setgt, HQ16, HVI16, HVI16>;
484 def: AccRRR_pat<V6_vgtw_and, And, setgt, HQ32, HVI32, HVI32>;
[all …]
DHexagonPatterns.td525 def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>;
545 def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>;
550 def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>;
558 def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>;
559 def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>;
568 def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>;
569 def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>;
578 def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>;
579 def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>;
587 def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>;
[all …]
/external/clang/test/CodeGen/
DBasicInstrs.c23 _Bool setgt(int X, int Y) { in setgt() function
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td100 // setgt-64.
111 // setlt-64 -> setgt-64.
DHexagonInstrInfoV3.td146 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
174 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
DHexagonInstrInfoVector.td228 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>;
232 def: vcmp_vi1_pat<A2_vcmphgt, setgt, V4I16, v4i1>;
286 def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
293 def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
75 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
75 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPU64InstrInfo.td175 // i64 setgt/setle:
216 def : Pat<(setgt R64C:$rA, R64C:$rB), I64GTr64.Fragment>;
217 //def : Pat<(setgt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
DSPUInstrInfo.td3023 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3028 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
3039 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
3043 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
3053 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3057 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
3068 (setgt (v8i16 VECREG:$rA),
3071 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
3082 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3085 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
[all …]
/external/clang/www/demo/
Dindex.cgi99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaInstrInfo.td203 defm CMOVGT : cmov_inst<0x66, "cmovgt", CmpOpFrag<(setgt node:$R, 0)>>;
217 def : Pat<(select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
381 def : Pat<(setgt GPRC:$X, GPRC:$Y), (CMPLT GPRC:$Y, GPRC:$X)>;
382 def : Pat<(setgt immUExt8:$X, GPRC:$Y), (CMPLTi GPRC:$Y, immUExt8:$X)>;
736 def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
779 def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
909 def : Pat<(brcond (setgt GPRC:$RA, 0), bb:$DISP),
934 def : Pat<(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP),
963 def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td1445 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1448 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1578 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1778 <(setgt CPU16Regs:$lhs, -32769),
1783 // setgt
1788 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
DMipsCondMov.td72 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
DMips64r6InstrInfo.td227 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.td1447 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1450 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1580 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1780 <(setgt CPU16Regs:$lhs, -32769),
1785 // setgt
1790 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
DMips64r6InstrInfo.td176 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
DMipsCondMov.td72 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreInstrInfo.td1173 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1237 // setge X, 0 is canonicalized to setgt X, -1
1238 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1244 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1247 def : Pat<(setgt GRRegs:$lhs, -1),
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td1236 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1300 // setge X, 0 is canonicalized to setgt X, -1
1301 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1307 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1310 def : Pat<(setgt GRRegs:$lhs, -1),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td1229 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1293 // setge X, 0 is canonicalized to setgt X, -1
1294 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1300 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1303 def : Pat<(setgt GRRegs:$lhs, -1),
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td161 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td622 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
657 def : BccSwapPat<setgt, BLT>;

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