Home
last modified time | relevance | path

Searched refs:shld (Results 1 – 25 of 61) sorted by relevance

123

/external/boringssl/win-x86_64/crypto/fipsmodule/
Dsha1-x86_64.asm2570 shld eax,eax,5
2584 shld ebp,ebp,5
2598 shld edx,edx,5
2613 shld ecx,ecx,5
2625 shld ebx,ebx,5
2639 shld eax,eax,5
2653 shld ebp,ebp,5
2668 shld edx,edx,5
2681 shld ecx,ecx,5
2695 shld ebx,ebx,5
[all …]
/external/boringssl/win-x86/crypto/fipsmodule/
Dsha1-586.asm2703 shld eax,eax,5
2718 shld edi,edi,5
2731 shld edx,edx,5
2745 shld ecx,ecx,5
2760 shld ebx,ebx,5
2775 shld eax,eax,5
2788 shld edi,edi,5
2802 shld edx,edx,5
2817 shld ecx,ecx,5
2832 shld ebx,ebx,5
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2006-01-19-ISelFoldingBug.ll2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
Dshift-coalesce.ll2 ; RUN: grep {shld.*CL}
Drot64.ll4 ; RUN: grep shld %t | count 2
/external/llvm/test/CodeGen/X86/
D2006-01-19-ISelFoldingBug.ll2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
Dx86-64-double-shifts-Oz-Os-O2.ll4 ; Verify that we generate shld insruction when we are optimizing for size,
26 ; Verify that we generate shld insruction when we are optimizing for size,
47 ; Verify that we do not generate shld insruction when we are not optimizing
Dx86-64-double-shifts-var.ll20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
30 ; CHECK-NOT: shld
Dshift-coalesce.ll2 ; RUN: grep "shld.*cl"
Dx86-64-double-precision-shift-left.ll4 ; of instructions with lower latencies instead of shld instruction.
Drot64.ll4 ; RUN: grep shld %t | count 2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dx86-64-double-shifts-Oz-Os-O2.ll5 ; Verify that we generate shld insruction when we are optimizing for size,
31 ; Verify that we generate shld insruction when we are optimizing for size,
56 ; Verify that we do not generate shld insruction when we are not optimizing
Dx86-64-double-shifts-var.ll23 ; double precision shift instructions we do not generate 'shld' or 'shrd'
33 ; CHECK-NOT: shld
Dshift-coalesce.ll2 ; RUN: grep "shld.*cl"
D2006-01-19-ISelFoldingBug.ll4 ; Check that the isel does not fold the shld, which already folds a load
Drot32.ll179 ; shld-label: xunp:
180 ; shld: shldl $25
Dx86-64-double-precision-shift-left.ll6 ; of instructions with lower latencies instead of shld instruction.
/external/llvm/test/MC/X86/
Dintel-syntax.s379 shld DX, BX define
380 shld DX, BX, CL define
381 shld DX, BX, 1 define
382 shld [RAX], BX label
383 shld [RAX], BX, CL label
Dx86-64.s378 shld %bx, %dx label
379 shld %cl, %bx, %dx label
380 shld $1, %bx, %dx label
381 shld %bx, (%rax) label
382 shld %cl, %bx, (%rax) label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/
Dx86-64.s374 shld %bx, %dx label
375 shld %cl, %bx, %dx label
376 shld $1, %bx, %dx label
377 shld %bx, (%rax) label
378 shld %cl, %bx, (%rax) label
Dintel-syntax.s441 shld DX, BX define
442 shld DX, BX, CL define
443 shld DX, BX, 1 define
444 shld [RAX], BX label
445 shld [RAX], BX, CL label
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td603 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
613 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
621 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
635 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
649 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
663 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
679 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
688 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
697 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
708 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td658 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
668 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
678 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
692 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
706 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
720 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
736 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
745 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
754 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
766 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/external/swiftshader/third_party/LLVM/test/MC/X86/
Dx86-64.s347 shld %bx,%bx label
348 shld $1, %bx,%bx label

123