Home
last modified time | relevance | path

Searched refs:subreg (Results 1 – 25 of 95) sorted by relevance

1234

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Ddetect-dead-lanes.mir9 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
31 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
45 # CHECK: %0:sreg_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
46 # CHECK: %1:sreg_128 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
47 # CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, $sgpr42, %subreg.sub0
56 # CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, %subreg.sub0
62 # CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
63 # CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub0
64 # CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub1
70 # CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, %subreg.sub1
[all …]
Dopt-sgpr-to-vgpr-copy.mir8 …GPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1
15 …GPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1
20 …P0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, %subreg.sub0, killed %{{[0-9]+}}, %subreg.s…
112 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1
120 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1
123 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1
136 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
211 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1
219 %18 = REG_SEQUENCE killed %16, %subreg.sub0, killed %17, %subreg.sub1
224 %23 = REG_SEQUENCE killed %21, %subreg.sub0, killed %22, %subreg.sub1
[all …]
Dspill-offset-calculation.ll55 ; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
83 ; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a
159 ; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
187 ; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a
/external/llvm/test/CodeGen/AMDGPU/
Ddetect-dead-lanes.mir42 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
102 %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
103 %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
104 %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, %subreg.sub0
113 %4 = INSERT_SUBREG %0, %3, %subreg.sub0
119 %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
120 %6 = EXTRACT_SUBREG %5, %subreg.sub0
121 %7 = EXTRACT_SUBREG %5, %subreg.sub1
127 %9 = EXTRACT_SUBREG %8, %subreg.sub1
130 %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/X86/
Dsubregister-index-operands.mir25 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
26 ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi
27 …; CHECK: $ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_…
29 %0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
30 %1 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi
31 $ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
Dsubreg-on-physreg.mir2 # This test ensures that an error is reported for subreg index on a physreg.
Dunknown-subregister-index-op.mir23 %0 = INSERT_SUBREG $edi, $al, %subreg.bit8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-constant.mir25 ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
33 ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1
41 ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO2]], %subreg.sub0, [[HI2]], %subreg.sub1
49 ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
Dinst-select-load-smrd.mir47 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
54 …ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
61 # GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
68 …ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
79 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
86 …ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/AMDGPU/
Dmir-canon-multi.mir18 %27:vreg_64 = REG_SEQUENCE %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1
23 … REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2, %subreg.sub2,…
/external/llvm/test/CodeGen/MIR/X86/
Dsubregister-index-operands.mir27 %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
28 %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
29 %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
Dunknown-subregister-index-op.mir24 %0 = INSERT_SUBREG %edi, %al, %subreg.bit8
/external/mesa3d/src/intel/compiler/
Dbrw_eu_validate.c467 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
477 ERROR_IF(subreg % exec_type_size != 0 && in general_restrictions_based_on_operand_types()
478 subreg % exec_type_size != 1, in general_restrictions_based_on_operand_types()
483 ERROR_IF(subreg % exec_type_size != 0, in general_restrictions_based_on_operand_types()
549 unsigned vstride, width, hstride, element_size, subreg; in general_restrictions_on_region_parameters() local
562 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst) in general_restrictions_on_region_parameters()
621 unsigned rowbase = subreg; in general_restrictions_on_region_parameters()
670 unsigned exec_size, unsigned element_size, unsigned subreg, in align1_access_mask() argument
674 unsigned rowbase = subreg; in align1_access_mask()
739 unsigned vstride, width, hstride, element_size, subreg; in region_alignment_rules() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dselect-cmp.mir103 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
134 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
165 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
196 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
227 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], %subreg.sub_8bit
258 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit
289 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], %subreg.sub_8bit
320 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], %subreg.sub_8bit
351 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], %subreg.sub_8bit
382 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], %subreg.sub_8bit
[all …]
Dselect-ext-x86-64.mir41 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit
114 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
139 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
164 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_16bit
189 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32bit
Dselect-ext.mir108 # ALL_NEXT: %3:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
147 # ALL_NEXT: %3:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
322 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
357 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
392 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
456 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit
Dx86_64-select-zext.mir168 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
261 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
323 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
351 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dregbankselect-reg_sequence.mir23 %0 = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1
Dselect-int-ext.mir36 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
81 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
175 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
Dselect-insert-extract.mir16 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
18 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
Dfp16-copy-gpr.mir51 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
54 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvirtregrewriter-subregliveness.mir13 # the first subreg copy.
43 # the first subreg copy.
65 # the first subreg copy. It is defined by this copy, but is not
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dcext-unnamed-global.mir31 %2:doubleregs = REG_SEQUENCE %0, %subreg.isub_lo, %1, %subreg.isub_hi
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td29 class RISCVReg64<RISCVReg32 subreg> : Register<""> {
30 let HWEncoding{4-0} = subreg.HWEncoding{4-0};
31 let SubRegs = [subreg];
33 let AsmName = subreg.AsmName;
34 let AltNames = subreg.AltNames;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpeephole.mir38 %6 = SUBREG_TO_REG %5, 0, %subreg.sub_32bit

1234