Searched refs:swc1 (Results 1 – 25 of 155) sorted by relevance
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/external/llvm/test/CodeGen/Mips/ |
D | fastcc.ll | 227 ; CHECK: swc1 $f0 228 ; CHECK: swc1 $f1 229 ; CHECK: swc1 $f2 230 ; CHECK: swc1 $f3 231 ; CHECK: swc1 $f4 232 ; CHECK: swc1 $f5 233 ; CHECK: swc1 $f6 234 ; CHECK: swc1 $f7 235 ; CHECK: swc1 $f8 236 ; CHECK: swc1 $f9 [all …]
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D | sint-fp-store_pattern.ll | 10 ; 32: swc1 $f[[R0]], 21 ; 32: swc1 $f[[R0]], 24 ; 64: swc1 $f[[R0]],
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D | micromips-lwc1-swc1.ll | 39 ; MM32: swc1 $f12, 0($[[R3]]) 45 ; MM64: swc1 $f12, 0($[[R3]])
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D | mips64fpldst.ll | 41 ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) 44 ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
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D | no-odd-spreg.ll | 31 ; ODDSPREG-NOT: swc1 36 ; NOODDSPREG: swc1 $[[T0]],
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D | fp-indexed-ls.ll | 114 ; MIPS32R1-DAG: swc1 $[[T0]], 0($[[T1]]) 121 ; MIPS32R6-DAG: swc1 $[[T0]], 0($[[T1]]) 128 ; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
D | fastcc.ll | 226 ; CHECK-DAG: swc1 $f0 227 ; CHECK-DAG: swc1 $f1 228 ; CHECK-DAG: swc1 $f2 229 ; CHECK-DAG: swc1 $f3 230 ; CHECK-DAG: swc1 $f4 231 ; CHECK-DAG: swc1 $f5 232 ; CHECK-DAG: swc1 $f6 233 ; CHECK-DAG: swc1 $f7 234 ; CHECK-DAG: swc1 $f8 235 ; CHECK-DAG: swc1 $f9 [all …]
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D | sint-fp-store_pattern.ll | 10 ; 32: swc1 $f[[R0]], 21 ; 32: swc1 $f[[R0]], 24 ; 64: swc1 $f[[R0]],
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D | mips64fpldst.ll | 39 ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) 42 ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
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D | no-odd-spreg.ll | 35 ; ODDSPREG-NOT: swc1 39 ; NOODDSPREG-NOT: swc1 $[[T0]],
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D | fp-indexed-ls.ll | 114 ; MIPS32R1-DAG: swc1 $[[T0]], 0($[[T1]]) 121 ; MIPS32R6-DAG: swc1 $[[T0]], 0($[[T1]]) 128 ; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
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D | micromips-lwc1-swc1.ll | 30 ; MM32: swc1 $f12, 0($[[R3]])
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/external/llvm/test/CodeGen/Mips/cconv/ |
D | arguments-hard-float.ll | 120 ; ALL-DAG: swc1 $f12, 4([[R1]]) 121 ; O32-DAG: swc1 $f14, 8([[R1]]) 122 ; NEW-DAG: swc1 $f13, 8([[R1]]) 129 ; NEW-DAG: swc1 $f14, 12([[R1]]) 131 ; NEW-DAG: swc1 $f15, 16([[R1]]) 135 ; O32-DAG: swc1 [[F1]], 20([[R1]]) 136 ; NEW-DAG: swc1 $f16, 20([[R1]]) 138 ; O32-DAG: swc1 [[F1]], 24([[R1]]) 139 ; NEW-DAG: swc1 $f17, 24([[R1]]) 141 ; O32-DAG: swc1 [[F1]], 28([[R1]]) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/ |
D | arguments-hard-float.ll | 120 ; ALL-DAG: swc1 $f12, 4([[R1]]) 121 ; O32-DAG: swc1 $f14, 8([[R1]]) 122 ; NEW-DAG: swc1 $f13, 8([[R1]]) 129 ; NEW-DAG: swc1 $f14, 12([[R1]]) 131 ; NEW-DAG: swc1 $f15, 16([[R1]]) 135 ; O32-DAG: swc1 [[F1]], 20([[R1]]) 136 ; NEW-DAG: swc1 $f16, 20([[R1]]) 138 ; O32-DAG: swc1 [[F1]], 24([[R1]]) 139 ; NEW-DAG: swc1 $f17, 24([[R1]]) 141 ; O32-DAG: swc1 [[F1]], 28([[R1]]) [all …]
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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | bitcast.ll | 41 ; MIPS32-OM1: swc1 68 ; MIPS32-O2: swc1 $f13, {{.*}} 69 ; MIPS32-O2: swc1 $f12, {{.*}} 92 ; MIPS32: swc1 $f{{[0-9]+}}, {{.*}} 93 ; MIPS32: swc1 $f{{[0-9]+}}, {{.*}}
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D | fp.load_store.ll | 64 ; MIPS32: swc1 $f{{.*}},0{{.*}} 67 ; MIPS32O2: swc1 $f{{.*}},0(a0) 99 ; MIPS32: swc1 $f{{.*}},0{{.*}} 103 ; MIPS32O2: swc1 $f{{.*}},0{{.*}}
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
D | mips-memory-instructions.s | 12 # CHECK: swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4] 19 swc1 $f2, 16($5)
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D | nacl-mask.s | 116 swc1 $f0, 0($4) 143 # CHECK-NEXT: swc1 $f0, 0($4)
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/external/llvm/test/MC/Mips/ |
D | mips-memory-instructions.s | 12 # CHECK: swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4] 19 swc1 $f2, 16($5)
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/external/libjpeg-turbo/simd/mips/ |
D | jsimd_dspr2.S | 4163 swc1 f2, 0(a2) 4164 swc1 f4, 4(a2) 4165 swc1 f6, 8(a2) 4167 swc1 f8, 12(a2) 4168 swc1 f10, 16(a2) 4169 swc1 f12, 20(a2) 4170 swc1 f14, 24(a2) 4171 swc1 f16, 28(a2) 4206 swc1 f2, 32(a2) 4207 swc1 f4, 36(a2) [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
D | mips64fpldst.ll | 37 ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) 40 ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | overflt.ll | 25 ; CHECK: swc1 $f[[REG_FPCONST]], 0($[[REG_Y_IDX]]) 45 ; CHECK-DAG: swc1 $f[[Y_IDX]], 0($[[REG_RESULT]])
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/external/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | overflt.ll | 25 ; CHECK: swc1 $f[[REG_FPCONST]], 0($[[REG_Y_IDX]]) 45 ; CHECK-DAG: swc1 $f[[Y_IDX]], 0($[[REG_RESULT]])
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/external/capstone/suite/MC/Mips/ |
D | mips-memory-instructions.s.cs | 7 0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($5)
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/external/llvm/test/MC/Mips/mips1/ |
D | valid.s | 115 swc1 $f6,-8465($24) 173 swc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xe4,0x40,A,A]
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