/external/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-add-sub.ll | 164 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a) 171 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a) 185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b) 192 %1 = tail call <1 x double> @llvm.aarch64.neon.fmax.v1f64(<1 x double> %a, <1 x double> %b) 199 %1 = tail call <1 x double> @llvm.aarch64.neon.fmin.v1f64(<1 x double> %a, <1 x double> %b) 206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b) 213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b) 220 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a) 231 declare <1 x double> @llvm.fabs.v1f64(<1 x double>) 232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>) [all …]
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D | arm64-extract_subvector.ll | 45 define <1 x double> @v1f64(<2 x double> %a) nounwind { 46 ; CHECK-LABEL: v1f64:
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D | vector-fcopysign.ll | 31 ;============ v1f64 42 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0) 52 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) 56 declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
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D | arm64-neon-simd-shift.ll | 635 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double> %a, i32 64) 642 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double> %a, i32 64) 649 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64> %a, i32 64) 656 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64> %a, i32 64) 660 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32) 661 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32) 662 declare <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32) 663 declare <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)
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D | arm64-indexed-vector-ldst.ll | 849 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 858 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 864 declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) 1101 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d… 1110 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d… 1116 declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) 1353 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 1362 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 1368 declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f… 1604 %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A) [all …]
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D | arm64-ld1.ll | 296 %tmp2 = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 305 %tmp2 = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A) 314 %tmp2 = call %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 318 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) nounwind readonly 319 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) nounwind readonly 320 declare %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double*) nounwind readonly 1049 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double*) nounwind readonly 1089 %val = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %addr) 1156 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double*) nounwind readonly 1196 %val = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %addr) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-add-sub.ll | 164 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a) 171 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a) 185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b) 192 %1 = tail call <1 x double> @llvm.aarch64.neon.fmax.v1f64(<1 x double> %a, <1 x double> %b) 199 %1 = tail call <1 x double> @llvm.aarch64.neon.fmin.v1f64(<1 x double> %a, <1 x double> %b) 206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b) 213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b) 220 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a) 231 declare <1 x double> @llvm.fabs.v1f64(<1 x double>) 232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>) [all …]
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D | arm64-extract_subvector.ll | 45 define <1 x double> @v1f64(<2 x double> %a) nounwind { 46 ; CHECK-LABEL: v1f64:
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D | vector-fcopysign.ll | 31 ;============ v1f64 42 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0) 52 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) 56 declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
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D | arm64-neon-simd-shift.ll | 635 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double> %a, i32 64) 642 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double> %a, i32 64) 649 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64> %a, i32 64) 656 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64> %a, i32 64) 660 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32) 661 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32) 662 declare <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32) 663 declare <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)
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D | arm64-indexed-vector-ldst.ll | 849 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 858 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 864 declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) 1101 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d… 1110 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d… 1116 declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) 1353 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 1362 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 1368 declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f… 1604 %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A) [all …]
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D | arm64-ld1.ll | 296 %tmp2 = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 305 %tmp2 = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A) 314 %tmp2 = call %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 318 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) nounwind readonly 319 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) nounwind readonly 320 declare %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double*) nounwind readonly 1049 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double*) nounwind readonly 1089 %val = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %addr) 1156 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double*) nounwind readonly 1196 %val = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %addr) [all …]
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 115 v1f64 = 60, // 1 x f64 enumerator 244 SimpleTy == MVT::v1f64); in is64BitVector() 364 case v1f64: in getVectorElementType() 425 case v1f64: return 1; in getVectorNumElements() 477 case v1f64: return 64; in getSizeInBits() 656 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
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/external/clang/test/CodeGen/ |
D | systemz-abi-vector.c | 25 typedef __attribute__((vector_size(8))) double v1f64; typedef 118 v1f64 pass_v1f64(v1f64 arg) { return arg; } in pass_v1f64()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 2973 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3000 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3027 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3054 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3081 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3108 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3135 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3162 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3189 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 3210 VT == MVT::v1f64) { in Select() [all …]
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D | AArch64InstrInfo.td | 1641 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>; 1784 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1945 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2277 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>; 2355 def : Pat<(store (v1f64 FPR64:$Rt), 2488 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2636 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2690 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2879 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))), 2907 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), [all …]
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D | AArch64CallingConvention.td | 77 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 86 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 117 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 176 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 186 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 206 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 2762 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2789 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2816 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2843 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2870 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2897 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2924 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2951 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2978 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select() 2999 VT == MVT::v1f64) { in Select() [all …]
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D | AArch64InstrInfo.td | 1434 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>; 1577 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1738 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2059 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>; 2152 def : Pat<(store (v1f64 FPR64:$Rt), 2249 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2355 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2409 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2591 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))), 2619 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), [all …]
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D | AArch64CallingConvention.td | 73 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 82 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 111 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 162 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 172 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 191 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
D | MachineValueType.h | 157 v1f64 = 93, // 1 x f64 enumerator 347 SimpleTy == MVT::v2f32 || SimpleTy == MVT::v1f64); in is64BitVector() 507 case v1f64: in getVectorElementType() 609 case v1f64: in getVectorNumElements() 687 case v1f64: in getSizeInBits() 897 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | ValueTypes.cpp | 189 case MVT::v1f64: return "v1f64"; in getEVTString() 270 case MVT::v1f64: return VectorType::get(Type::getDoubleTy(Context), 1); in getTypeForEVT()
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 192 case MVT::v1f64: return "v1f64"; in getEVTString() 270 case MVT::v1f64: return VectorType::get(Type::getDoubleTy(Context), 1); in getTypeForEVT()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenDAGISel.inc | 1297 /* 2651*/ OPC_CheckChild1Type, MVT::v1f64, 1306 …// Src: (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ … 1307 …// Dst: (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wexte… 1313 …// Src: (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ … 1314 …// Dst: (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xexte… 1332 …// Src: (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed7s32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, simm7s4… 1333 …:[i32] } FPR64:{ *:[v1f64] }:$Rt, ssub:{ *:[i32] }), (CPYi32:{ *:[i32] } (SUBREG_TO_REG:{ *:[f128]… 1339 …// Src: (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:… 1340 … // Dst: (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) 1976 /* 4035*/ OPC_CheckChild0Type, MVT::v1f64, [all …]
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D | AArch64GenCallingConv.inc | 230 LocVT == MVT::v1f64 || 280 LocVT == MVT::v1f64 || 474 LocVT == MVT::v1f64 || 526 LocVT == MVT::v1f64 || 612 LocVT == MVT::v1f64 || 924 LocVT == MVT::v1f64 ||
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