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Searched refs:v2i16 (Results 1 – 25 of 143) sorted by relevance

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/external/clang/test/CodeGen/
Dbuiltins-mips.c12 typedef short v2i16 __attribute__ ((vector_size(4))); typedef
17 v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c; in foo()
352 v2i16_a = (v2i16) {0xffff, 0x2468}; in foo()
353 v2i16_b = (v2i16) {0x1234, 0x1111}; in foo()
356 v2i16_a = (v2i16) {0xffff, 0x2468}; in foo()
357 v2i16_b = (v2i16) {0x1234, 0x1111}; in foo()
392 v2i16_b = (v2i16) {0xffff, 0x1555}; in foo()
393 v2i16_c = (v2i16) {0x1234, 0x3322}; in foo()
397 v2i16_b = (v2i16) {0xffff, 0x1555}; in foo()
398 v2i16_c = (v2i16) {0x1234, 0x3322}; in foo()
[all …]
Dppc64-vector.c3 typedef short v2i16 __attribute__((vector_size (4))); typedef
13 v2i16 test_v2i16(v2i16 x) in test_v2i16()
Dsystemz-abi-vector.c16 typedef __attribute__((vector_size(4))) short v2i16; typedef
70 v2i16 pass_v2i16(v2i16 arg) { return arg; } in pass_v2i16()
Dx86_32-arguments-darwin.c217 typedef unsigned short v2i16 __attribute__((__vector_size__(4))); typedef
221 v2i16 f54(v2i16 arg) { return arg+arg; } in f54()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.exp.compr.ll6 declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #0
98 …call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 0, <2 x i16> zeroinitializer, <2 x i16> zeroinit…
99 …call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 0, <2 x i16> zeroinitializer, <2 x i16> zeroinit…
108 …call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 1, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i…
117 …call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 12, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, …
126 …call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, …
135 …call void @llvm.amdgcn.exp.compr.v2i16(i32 7, i32 15, <2 x i16> <i16 5, i16 5>, <2 x i16> <i16 5, …
136 …call void @llvm.amdgcn.exp.compr.v2i16(i32 7, i32 15, <2 x i16> <i16 5, i16 5>, <2 x i16> <i16 5, …
146 …call void @llvm.amdgcn.exp.compr.v2i16(i32 8, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, …
147 …call void @llvm.amdgcn.exp.compr.v2i16(i32 8, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, …
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td18 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
40 defm : bitconvert_32<v2i16, i32>;
69 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
72 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
268 def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
339 def: Pat<(v2i16 (trunc V2I32:$Rs)),
360 // Sign extends a v2i16 into a v2i32.
361 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
365 // Multiplies two v2i16 and returns a v2i32. We are using here the
370 // Multiplies two v2i16 vectors: as Hexagon does not have a multiply
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc827 …// (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } …
1198 …// (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } …
1488 …// (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v…
2789 …// (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v…
2811 …// (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v…
2862 …// (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ …
2871 …// (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ …
4307 … (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$…
4328 …intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$im…
4381 … *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:…
[all …]
DMipsGenDAGISel.inc542 /* 884*/ OPC_CheckChild1Type, MVT::v2i16,
554 …// Src: (st DSPR:{ *:[v2i16] }:$val, addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predic…
555 …// Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$val, GPR32:{ *:[i32] }), addr:{ *:[i…
1327 /* 2361*/ /*SwitchType*/ 25, MVT::v2i16,// ->2388
1335 MVT::v2i16, 2/*#Ops*/, 4, 5,
1336 …// Src: (ld:{ *:[v2i16] } addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> -…
1337 … // Dst: (COPY_TO_REGCLASS:{ *:[v2i16] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
7629 …rinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$…
7630 … // Dst: (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7636 …rinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$…
[all …]
/external/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll39 ; v2i16
86 ; v2i16
121 ; v2i8 x v2i16
136 ; v2i16
137 ; v2i16 x v2i32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll39 ; v2i16
86 ; v2i16
121 ; v2i8 x v2i16
136 ; v2i16
137 ; v2i16 x v2i32
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1328 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1330 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1332 def : BitconvertPat<f32, v2i16, FGR32, DSPR>;
1334 def : BitconvertPat<v2i16, f32, DSPR, FGR32>;
1337 def : DSPPat<(v2i16 (load addr:$a)),
1338 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1341 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1351 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1352 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1353 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
[all …]
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1317 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1319 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1322 def : DSPPat<(v2i16 (load addr:$a)),
1323 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1326 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1336 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1337 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1338 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1339 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1340 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dbitreverse.ll6 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
11 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
248 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h79 v2i16 = 31, // 2 x i16 enumerator
234 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
335 case v2i16: in getVectorElementType()
413 case v2i16: in getVectorNumElements()
463 case v2i16: in getSizeInBits()
615 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td16 CCIfType<[i32,v2i16,v4i8],
40 CCIfType<[i32,v2i16,v4i8],
68 CCIfType<[i32,v2i16,v4i8],
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h59 v2i16 = 17, // 2 x i16 enumerator
195 case v2i16: in getVectorElementType()
233 case v2i16: in getVectorNumElements()
259 case v2i16: return 32; in getSizeInBits()
346 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td166 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
216 def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
343 def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
401 def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
415 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
422 def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
427 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
433 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
548 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
DSIInstructions.td813 (v2i16 (EXTRACT_SUBREG v4i16:$vec, sub0))
818 (v2i16 (EXTRACT_SUBREG v4i16:$vec, sub1))
846 def : BitConvert <v2i16, i32, SReg_32>;
847 def : BitConvert <i32, v2i16, SReg_32>;
850 def : BitConvert <v2i16, v2f16, SReg_32>;
851 def : BitConvert <v2f16, v2i16, SReg_32>;
854 def : BitConvert <v2i16, f32, SReg_32>;
855 def : BitConvert <f32, v2i16, SReg_32>;
1470 (v2i16 (build_vector (i16 0), i16:$src1)),
1471 (v2i16 (COPY_TO_REGCLASS (S_LSHL_B32 i16:$src1, (i16 16)), SReg_32_XM0))
[all …]
DAMDGPUCallingConv.td109 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
115 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
126 CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h82 v2i16 = 34, // 2 x i16 enumerator
338 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
452 case v2i16: in getVectorElementType()
588 case v2i16: in getVectorNumElements()
667 case v2i16: in getSizeInBits()
856 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp327 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
330 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
351 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
354 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
368 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
371 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
382 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
385 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dbitreverse.ll5 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
16 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-const-02.ll49 ; Test an all-zeros v2i16 that gets promoted to v8i16.
57 ; Test a mixed v2i16 that gets promoted to v8i16 (mask 0xc000).
/external/llvm/test/CodeGen/SystemZ/
Dvec-const-02.ll49 ; Test an all-zeros v2i16 that gets promoted to v8i16.
57 ; Test a mixed v2i16 that gets promoted to v8i16 (mask 0xc000).

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