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Searched refs:v4f16 (Results 1 – 25 of 78) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vfloatintrinsics.ll7 %v4f16 = type <4 x half>
16 define %v4f16 @test_v4f16.sqrt(%v4f16 %a) {
27 %1 = call %v4f16 @llvm.sqrt.v4f16(%v4f16 %a)
28 ret %v4f16 %1
100 define %v4f16 @test_v4f16.fma(%v4f16 %a, %v4f16 %b, %v4f16 %c) {
110 %1 = call %v4f16 @llvm.fma.v4f16(%v4f16 %a, %v4f16 %b, %v4f16 %c)
111 ret %v4f16 %1
128 define %v4f16 @test_v4f16.fabs(%v4f16 %a) {
139 %1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a)
140 ret %v4f16 %1
[all …]
Dfp16-vector-load-store.ll43 ; Load to one lane of v4f16
63 ; Simple store of v4f16
81 ; Store from one lane of v4f16
180 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
181 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
182 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
183 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
184 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
185 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <…
193 ; Load 2 x v4f16 with de-interleaving
[all …]
Dfp16_intrinsic_vector_2op.ll3 declare <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half>, <4 x half>)
5 declare <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half>, <4 x half>)
7 declare <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half>, <4 x half>)
9 declare <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half>, <4 x half>)
11 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
37 %vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %b)
55 %vpminnm2.i = tail call <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half> %a, <4 x half> %b)
73 %vpmaxnm2.i = tail call <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half> %a, <4 x half> %b)
91 %vabdh_f16 = tail call <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half> %a, <4 x half> %b)
110 %abs = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %sub)
Dfp16_intrinsic_vector_1op.ll3 declare <4 x half> @llvm.nearbyint.v4f16(<4 x half>)
5 declare <4 x half> @llvm.sqrt.v4f16(<4 x half>)
13 %vrndi1.i = tail call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %a)
31 %vsqrt.i = tail call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)
Dfp16-vector-nvcast.ll3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
Dfp16_intrinsic_lane.ll4 declare <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half>, <4 x half>)
6 declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
17 %fmla3 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %lane1, <4 x half> %a)
39 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %lane1, <4 x half> %b, <4 x half> %a)
62 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %vecinit3, <4 x half> %a) #4
107 %fmla3 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %sub, <4 x half> %lane1, <4 x half> %a)
132 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %lane1, <4 x half> %sub, <4 x half> %a)
158 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %sub, <4 x half> %vecinit3, <4 x half> %a) #4
265 …%vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %shuffle…
285 …%vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %shuffle…
[all …]
Dfp16_intrinsic_vector_3op.ll3 declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
11 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)
/external/llvm/test/CodeGen/AArch64/
Dfp16-vector-load-store.ll43 ; Load to one lane of v4f16
63 ; Simple store of v4f16
81 ; Store from one lane of v4f16
102 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
103 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
104 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
105 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
106 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
107 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <…
115 ; Load 2 x v4f16 with de-interleaving
[all …]
Dfp16-vector-nvcast.ll3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.image.d16.dim.ll28 …%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsr…
38 …%tex = call <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32 15, i32 %s, i32 %t, i32 %mip, …
83 …call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %data, i32 15, i32 %s, i32 %t, <8 x i32…
97 …call void @llvm.amdgcn.image.store.mip.1d.v4f16.i32(<4 x half> %data, i32 15, i32 %s, i32 %mip, <8…
103 declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
104 declare <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32, i32, i32, i32, <8 x i32>, i32, i32…
109 declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32, i32, i32, <8 x i32>, i32, i32) …
110 declare void @llvm.amdgcn.image.store.mip.1d.v4f16.i32(<4 x half>, i32, i32, i32, <8 x i32>, i32, i…
Dllvm.amdgcn.image.gather4.d16.dim.ll10 …%tex = call <4 x half> @llvm.amdgcn.image.gather4.b.2d.v4f16.f32.f32(i32 4, float %bias, float %s,…
15 declare <4 x half> @llvm.amdgcn.image.gather4.b.2d.v4f16.f32.f32(i32, float, float, float, <8 x i32…
Dllvm.amdgcn.buffer.load.format.d16.ll34 …%data = call <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0,…
41 declare <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32>, i32, i32, i1, i1)
Dllvm.amdgcn.tbuffer.load.d16.ll34 …%data = call <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 …
41 declare <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
Dllvm.amdgcn.buffer.store.format.d16.ll51 …call void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i3…
57 declare void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i1, i1)
Dllvm.amdgcn.image.sample.d16.dim.ll28 …%tex = call <4 x half> @llvm.amdgcn.image.sample.b.2d.v4f16.f32.f32(i32 15, float %bias, float %s,…
35 declare <4 x half> @llvm.amdgcn.image.sample.b.2d.v4f16.f32.f32(i32, float, float, float, <8 x i32>…
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h108 v4f16 = 53, // 4 x f16 enumerator
243 SimpleTy == MVT::v4f16 || SimpleTy == MVT::v2f32 || in is64BitVector()
357 case v4f16: in getVectorElementType()
408 case v4f16: in getVectorNumElements()
475 case v4f16: in getSizeInBits()
645 if (NumElements == 4) return MVT::v4f16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfp16-intrinsic-vector-2op.ll4 declare <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half>, <4 x half>)
19 %vpadd_v2.i = tail call <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half> %a, <4 x half> %b)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2961 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2988 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3015 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3042 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3069 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3096 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3123 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3150 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3177 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3201 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
[all …]
DAArch64CallingConvention.td32 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
77 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
86 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
101 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
117 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
176 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
186 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
206 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2750 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2777 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2804 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2831 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2858 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2885 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2912 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2939 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2966 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2990 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
[all …]
DAArch64CallingConvention.td31 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
73 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
82 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
96 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
111 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
162 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
172 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
191 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h150 v4f16 = 86, // 4 x f16 enumerator
346 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || in is64BitVector()
492 case v4f16: in getVectorElementType()
575 case v4f16: in getVectorNumElements()
685 case v4f16: in getSizeInBits()
886 if (NumElements == 4) return MVT::v4f16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/FuzzMutate/
DOperationsTest.cpp97 Constant *v4f16 = ConstantVector::getSplat(4, f16); in TEST() local
125 EXPECT_FALSE(AnyInt.matches({}, v4f16)); in TEST()
136 EXPECT_FALSE(AnyFP.matches({}, v4f16)); in TEST()
155 EXPECT_TRUE(AnyVec.matches({}, v4f16)); in TEST()
167 EXPECT_FALSE(First.matches({v4f16, f64}, f64)); in TEST()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenDAGISel.inc606 /* 1163*/ OPC_CheckChild0Type, MVT::v4f16,
627 …// Src: (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<<P:Predi…
628 …Dst: (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[…
1216 /* 2475*/ OPC_CheckChild1Type, MVT::v4f16,
1226 …// Src: (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ …
1227 …// Dst: (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wexte…
1233 …// Src: (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ …
1234 …// Dst: (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xexte…
1240 …// Src: (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:…
1241 … // Dst: (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc12475 /* 26451*/ /*SwitchType*/ 11, MVT::v4f16,// ->26464
12476 /* 26453*/ OPC_CheckChild1Type, MVT::v4f16,
12479 MVT::v4f16, 1/*#Ops*/, 0,
12480 …// Src: (intrinsic_wo_chain:{ *:[v4f16] } 1103:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) - Complexity =…
12481 // Dst: (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15006 /* 31671*/ OPC_CheckChild1Type, MVT::v4f16,
15018 …// Src: (intrinsic_wo_chain:{ *:[v4i16] } 1025:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32]…
15019 // Dst: (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
15070 /* 31803*/ OPC_CheckChild1Type, MVT::v4f16,
15082 …// Src: (intrinsic_wo_chain:{ *:[v4i16] } 1026:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32]…
[all …]

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