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Searched refs:v64i1 (Results 1 – 25 of 30) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td343 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
346 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
349 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
352 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
397 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
400 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
455 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
458 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
469 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
480 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
[all …]
DX86CallingConv.td94 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
95 CCIfType<[v64i1], CCPromoteToType<i64>>,
172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
173 CCIfType<[v64i1], CCPromoteToType<i64>>,
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
532 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
808 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
DX86RegisterInfo.td580 def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
588 def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
DX86FrameLowering.cpp1996 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in assignCalleeSavedSpillSlots()
2069 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in spillCalleeSavedRegisters()
2150 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in restoreCalleeSavedRegisters()
DX86ISelLowering.cpp1486 addRegisterClass(MVT::v64i1, &X86::VK64RegClass); in X86TargetLowering()
1488 for (auto VT : { MVT::v32i1, MVT::v64i1 }) { in X86TargetLowering()
1504 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); in X86TargetLowering()
1506 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom); in X86TargetLowering()
2239 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) { in lowerMasksToReg()
2381 assert(VA.getValVT() == MVT::v64i1 && in LowerReturn()
2549 assert(VA.getValVT() == MVT::v64i1 && in getv64i1Argument()
2589 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi); in getv64i1Argument()
2603 if (ValVT == MVT::v64i1) { in lowerRegToMasks()
2679 assert(VA.getValVT() == MVT::v64i1 && in LowerCallResult()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h64 v64i1 = 18, // 64 x i1 enumerator
322 case v64i1: in getVectorElementType()
380 case v64i1: in getVectorNumElements()
470 case v64i1: in getSizeInBits()
598 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
DValueTypes.td41 def v64i1 : ValueType<64 , 18>; // 64 x i1 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h66 v64i1 = 20, // 64 x i1 enumerator
344 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
426 case v64i1: in getVectorElementType()
528 case v64i1: in getVectorNumElements()
680 case v64i1: in getSizeInBits()
838 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp146 case MVT::v64i1: return "v64i1"; in getEVTString()
227 case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp150 case MVT::v64i1: return "v64i1"; in getEVTString()
228 case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td290 [v64i1, v128i1, v64i1]>;
292 [v32i1, v64i1, v32i1]>;
DHexagonISelLoweringHVX.cpp42 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
52 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-regcall-Mask.ll6 ; Test regcall when receiving arguments of v64i1 type
95 ; Test regcall when passing arguments of v64i1 type
217 ; Test regcall when returning v64i1 type
233 ; Test regcall when processing result of v64i1 type
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td42 def v64i1 : ValueType<64 , 20>; // 64 x i1 vector value
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp78 case MVT::v64i1: return "MVT::v64i1"; in getEnumName()
/external/llvm/lib/Target/X86/
DX86CallingConv.td51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
328 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
601 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
DX86RegisterInfo.td517 def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
525 def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
DX86InstrAVX512.td1988 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2020 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2021 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2082 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2084 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2158 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2235 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2336 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2375 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2441 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
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DX86ISelLowering.cpp1391 MVT::v16i1, MVT::v32i1, MVT::v64i1 }) in X86TargetLowering()
1417 addRegisterClass(MVT::v64i1, &X86::VK64RegClass); in X86TargetLowering()
1420 setOperationAction(ISD::ADD, MVT::v64i1, Expand); in X86TargetLowering()
1422 setOperationAction(ISD::SUB, MVT::v64i1, Expand); in X86TargetLowering()
1424 setOperationAction(ISD::MUL, MVT::v64i1, Expand); in X86TargetLowering()
1427 setOperationAction(ISD::SETCC, MVT::v64i1, Custom); in X86TargetLowering()
1433 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); in X86TargetLowering()
1437 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom); in X86TargetLowering()
1445 setOperationAction(ISD::SELECT, MVT::v64i1, Custom); in X86TargetLowering()
1456 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom); in X86TargetLowering()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc524 if (LocVT == MVT::v64i1) {
854 if (LocVT == MVT::v64i1) {
1532 if (LocVT == MVT::v64i1) {
1931 if (LocVT == MVT::v64i1) {
2363 if (LocVT == MVT::v64i1) {
2748 if (LocVT == MVT::v64i1) {
3061 if (LocVT == MVT::v64i1) {
3634 if (LocVT == MVT::v64i1) {
3834 if (LocVT == MVT::v64i1) {
DX86GenGlobalISel.inc3751 … (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KANDQrr:{ *:[v64i1] …
4829 …// (or:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KORQrr:{ *:[v64i1] …
5654 … (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KXORQrr:{ *:[v64i1] …
5830 …// (bitconvert:{ *:[i64] } VK64:{ *:[v64i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i64] } VK64:{ *:[v…
6981 …// (bitconvert:{ *:[v64i1] } GR64:{ *:[i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v64i1] } GR64:{ *:…
11267 …// (sext:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) => (VPMOVM2BZrr:{ *:[v64i8] } VK64:{ *:[v64i1] }…
DX86GenFastISel.inc1651 case MVT::v64i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v64i1_r(RetVT, Op0, Op0IsKill);
5811 if (RetVT.SimpleTy != MVT::v64i1)
5867 case MVT::v64i1: return fastEmit_ISD_AND_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6692 if (RetVT.SimpleTy != MVT::v64i1)
6748 case MVT::v64i1: return fastEmit_ISD_OR_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
8148 if (RetVT.SimpleTy != MVT::v64i1)
8204 case MVT::v64i1: return fastEmit_ISD_XOR_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
9657 if (RetVT.SimpleTy != MVT::v64i1)
9670 case MVT::v64i1: return fastEmit_X86ISD_KADD_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
9718 …case MVT::v64i1: return fastEmit_X86ISD_KORTEST_MVT_v64i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp85 case MVT::v64i1: return "MVT::v64i1"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td174 def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsics.td202 def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1

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