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Searched refs:v8f16 (Results 1 – 25 of 73) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vfloatintrinsics.ll8 %v8f16 = type <8 x half>
30 define %v8f16 @test_v8f16.sqrt(%v8f16 %a) {
37 %1 = call %v8f16 @llvm.sqrt.v8f16(%v8f16 %a)
38 ret %v8f16 %1
113 define %v8f16 @test_v8f16.fma(%v8f16 %a, %v8f16 %b, %v8f16 %c) {
119 %1 = call %v8f16 @llvm.fma.v8f16(%v8f16 %a, %v8f16 %b, %v8f16 %c)
120 ret %v8f16 %1
142 define %v8f16 @test_v8f16.fabs(%v8f16 %a) {
149 %1 = call %v8f16 @llvm.fabs.v8f16(%v8f16 %a)
150 ret %v8f16 %1
[all …]
Dfp16-vector-load-store.ll53 ; Load to one lane of v8f16
72 ; Simple store of v8f16
130 ; Store from one lane of v8f16
186 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>*)
187 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>*)
188 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 …
189 declare void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*)
190 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
191 declare void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <…
247 ; Load 2 x v8f16 with de-interleaving
[all …]
Dfp16_intrinsic_vector_2op.ll4 declare <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half>, <8 x half>)
6 declare <8 x half> @llvm.aarch64.neon.fminnmp.v8f16(<8 x half>, <8 x half>)
8 declare <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half>, <8 x half>)
10 declare <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half>, <8 x half>)
12 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
46 %vmulx2.i = tail call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %b)
64 %vpminnm2.i = tail call <8 x half> @llvm.aarch64.neon.fminnmp.v8f16(<8 x half> %a, <8 x half> %b)
82 %vpmaxnm2.i = tail call <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half> %a, <8 x half> %b)
100 %vabdh_f16 = tail call <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half> %a, <8 x half> %b)
120 %abs = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %sub)
Dfp16_intrinsic_vector_1op.ll4 declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>)
6 declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
22 %vrndi1.i = tail call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)
40 %vsqrt.i = tail call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)
Dfp16-vector-nvcast.ll46 ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
57 ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
68 ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
79 ; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
Dfp16_intrinsic_lane.ll5 declare <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half>, <8 x half>)
7 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
28 %fmla3 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %lane1, <8 x half> %a)
50 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %lane1, <8 x half> %b, <8 x half> %a)
74 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %vecinit7, <8 x half> %a) #4
120 %fmla3 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %sub, <8 x half> %lane1, <8 x half> %a)
144 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %lane1, <8 x half> %sub, <8 x half> %a)
172 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %sub, <8 x half> %vecinit7, <8 x half> %a) #4
275 …%vmulx2.i = tail call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %shuffle…
295 …%vmulx2.i = tail call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %shuffle…
[all …]
Dfp16_intrinsic_vector_3op.ll4 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
20 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)
/external/llvm/test/CodeGen/AArch64/
Dfp16-vector-load-store.ll53 ; Load to one lane of v8f16
72 ; Simple store of v8f16
91 ; Store from one lane of v8f16
108 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>*)
109 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>*)
110 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 …
111 declare void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*)
112 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
113 declare void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <…
169 ; Load 2 x v8f16 with de-interleaving
[all …]
Dfp16-vector-nvcast.ll46 ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
57 ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
68 ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
79 ; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h109 v8f16 = 54, // 8 x f16 enumerator
251 SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 || in is128BitVector()
358 case v8f16: return f16; in getVectorElementType()
400 case v8f16: in getVectorNumElements()
487 case v8f16: in getSizeInBits()
646 if (NumElements == 8) return MVT::v8f16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2964 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2991 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3018 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3045 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3072 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3099 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3126 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3153 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3180 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3202 VT == MVT::v8f16) { in Select()
[all …]
DAArch64CallingConvention.td34 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
80 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
88 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
103 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
120 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
179 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
188 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
208 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
DAArch64InstrInfo.td1595 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1651 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1804 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1964 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2288 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2311 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>;
2403 def : Pat<(store (v8f16 FPR128:$Rt),
2433 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>;
2541 def : Pat<(store (v8f16 FPR128:$Rt),
2565 defm : VecStoreULane0Pat<store, v8f16, f16, hsub, STURHi>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2753 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2780 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2807 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2834 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2861 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2888 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2915 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2942 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2969 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2991 VT == MVT::v8f16) { in Select()
[all …]
DAArch64CallingConvention.td33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
76 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
84 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
98 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
114 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
165 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
174 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
193 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
DAArch64InstrInfo.td1388 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1444 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1597 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1757 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2070 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2180 def : Pat<(store (v8f16 FPR128:$Rt),
2278 def : Pat<(store (v8f16 FPR128:$Rt),
2372 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2426 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2797 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h151 v8f16 = 87, // 8 x f16 enumerator
355 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 || in is128BitVector()
493 case v8f16: in getVectorElementType()
559 case v8f16: in getVectorNumElements()
705 case v8f16: in getSizeInBits()
887 if (NumElements == 8) return MVT::v8f16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfp16-intrinsic-vector-1op.ll6 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
36 %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a) #3
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenDAGISel.inc137 /* 173*/ OPC_CheckChild0Type, MVT::v8f16,
153 …// Src: (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[iPTR] }), (ro_Wind…
154 …// Dst: (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), G…
163 …// Src: (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[iPTR] }), (ro_Xind…
164 …// Dst: (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), G…
173 …// Src: (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[iPTR] }), (am_inde…
174 …// Dst: (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GP…
183 …// Src: (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[iPTR] }), (am_unsc…
184 …// Dst: (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GP…
203 …// Src: (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Pred…
[all …]
DAArch64GenCallingConv.inc72 LocVT == MVT::v8f16 ||
252 LocVT == MVT::v8f16) {
299 LocVT == MVT::v8f16) {
495 LocVT == MVT::v8f16) {
544 LocVT == MVT::v8f16) {
626 LocVT == MVT::v8f16) {
836 LocVT == MVT::v8f16 ||
946 LocVT == MVT::v8f16) {
/external/clang/test/CodeGen/
Dbuiltins-mips-msa.c13 typedef __fp16 v8f16 __attribute__ ((vector_size(16))); typedef
44 v8f16 v8f16_a = (v8f16) {0.5, 1, 2, 3, 4, 5, 6, 7}; in test()
45 v8f16 v8f16_b = (v8f16) {1.5, 2, 3, 4, 5, 6, 7, 8}; in test()
46 v8f16 v8f16_r; in test()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc12482 /* 26464*/ /*SwitchType*/ 11, MVT::v8f16,// ->26477
12483 /* 26466*/ OPC_CheckChild1Type, MVT::v8f16,
12486 MVT::v8f16, 1/*#Ops*/, 0,
12487 …// Src: (intrinsic_wo_chain:{ *:[v8f16] } 1103:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) - Complexity =…
12488 // Dst: (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15036 /* 31733*/ OPC_CheckChild1Type, MVT::v8f16,
15048 …// Src: (intrinsic_wo_chain:{ *:[v8i16] } 1025:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32]…
15049 // Dst: (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
15100 /* 31865*/ OPC_CheckChild1Type, MVT::v8f16,
15112 …// Src: (intrinsic_wo_chain:{ *:[v8i16] } 1026:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32]…
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Dbitcast.ll56 ; are no operations for v8f16 to put in the way.
230 ; are no operations for v8f16 to put in the way.
354 ; are no operations for v8f16 to put in the way.
378 ; are no operations for v8f16 to put in the way.
401 ; are no operations for v8f16 to put in the way.
403 ; are no operations for v8f16 to put in the way.
423 ; are no operations for v8f16 to put in the way.
447 ; are no operations for v8f16 to put in the way.
471 ; are no operations for v8f16 to put in the way.
495 ; are no operations for v8f16 to put in the way.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dbitcast.ll56 ; are no operations for v8f16 to put in the way.
230 ; are no operations for v8f16 to put in the way.
354 ; are no operations for v8f16 to put in the way.
378 ; are no operations for v8f16 to put in the way.
401 ; are no operations for v8f16 to put in the way.
403 ; are no operations for v8f16 to put in the way.
423 ; are no operations for v8f16 to put in the way.
447 ; are no operations for v8f16 to put in the way.
471 ; are no operations for v8f16 to put in the way.
495 ; are no operations for v8f16 to put in the way.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.td164 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
180 CCIfType<[v2i64, v4i32, v8i16, v8f16,v16i8, v4f32], CCBitConvertToType<v2f64>>,
205 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
226 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,

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