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Searched refs:vn (Results 1 – 25 of 243) sorted by relevance

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/external/v8/src/arm64/
Dassembler-arm64.cc1820 void Assembler::NEON3DifferentL(const VRegister& vd, const VRegister& vn, in NEON3DifferentL() argument
1822 DCHECK(AreSameFormat(vn, vm)); in NEON3DifferentL()
1823 DCHECK((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) || in NEON3DifferentL()
1824 (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) || in NEON3DifferentL()
1825 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEON3DifferentL()
1826 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEON3DifferentL()
1830 format = SFormat(vn); in NEON3DifferentL()
1832 format = VFormat(vn); in NEON3DifferentL()
1834 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentL()
1837 void Assembler::NEON3DifferentW(const VRegister& vd, const VRegister& vn, in NEON3DifferentW() argument
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Dassembler-arm64.h1247 void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1253 void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1256 void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1259 void bit(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1262 void bsl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1265 void pmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1272 void mvn(const VRegister& vd, const VRegister& vn);
1279 void suqadd(const VRegister& vd, const VRegister& vn);
1282 void usqadd(const VRegister& vd, const VRegister& vn);
1285 void abs(const VRegister& vd, const VRegister& vn);
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Dmacro-assembler-arm64.h217 void Mov(const VRegister& vd, int vd_index, const VRegister& vn, in Mov() argument
220 mov(vd, vd_index, vn, vn_index); in Mov()
222 void Mov(const VRegister& vd, const VRegister& vn, int index) { in Mov() argument
224 mov(vd, vn, index); in Mov()
230 void Mov(const Register& rd, const VRegister& vn, int vn_index) { in Mov() argument
232 mov(rd, vn, vn_index); in Mov()
274 void MASM(const VRegister& vd, const VRegister& vn, const VRegister& vm, \
277 ASM(vd, vn, vm, vm_index); \
357 void MASM(const VRegister& vd, const VRegister& vn) { \
359 ASM(vd, vn); \
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/external/vixl/src/aarch64/
Dassembler-aarch64.cc315 const VRegister& vn, in NEONTable() argument
320 VIXL_ASSERT(vn.Is16B()); in NEONTable()
322 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
327 const VRegister& vn, in tbl() argument
330 NEONTable(vd, vn, vm, NEON_TBL_1v); in tbl()
335 const VRegister& vn, in tbl() argument
340 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbl()
341 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbl()
342 NEONTable(vd, vn, vm, NEON_TBL_2v); in tbl()
347 const VRegister& vn, in tbl() argument
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Dassembler-aarch64.h565 void tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
569 const VRegister& vn,
575 const VRegister& vn,
582 const VRegister& vn,
589 void tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm);
593 const VRegister& vn,
599 const VRegister& vn,
606 const VRegister& vn,
2171 void fmov(const Register& rd, const VRegister& vn, int index);
2174 void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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Dmacro-assembler-aarch64.h1323 void Fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fadd() argument
1326 fadd(vd, vn, vm); in Fadd()
1328 void Fccmp(const VRegister& vn,
1336 FPCCompareMacro(vn, vm, nzcv, cond, trap);
1338 void Fccmpe(const VRegister& vn, in Fccmpe() argument
1342 Fccmp(vn, vm, nzcv, cond, EnableTrap); in Fccmpe()
1344 void Fcmp(const VRegister& vn,
1349 FPCompareMacro(vn, vm, trap);
1351 void Fcmp(const VRegister& vn, double value, FPTrapFlags trap = DisableTrap);
1352 void Fcmpe(const VRegister& vn, double value);
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/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md1407 void abs(const VRegister& vd, const VRegister& vn)
1414 void add(const VRegister& vd, const VRegister& vn, const VRegister& vm)
1421 void addhn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
1428 void addhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
1435 void addp(const VRegister& vd, const VRegister& vn)
1442 void addp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
1449 void addv(const VRegister& vd, const VRegister& vn)
1456 void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm)
1470 void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm)
1477 void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm)
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-and-03.ll9 ; CHECK: vn %v24, %v24, [[REG]]
20 ; CHECK: vn %v24, %v24, [[REG]]
31 ; CHECK: vn %v24, %v24, [[REG]]
42 ; CHECK: vn %v24, %v24, [[REG]]
53 ; CHECK: vn %v24, %v24, [[REG]]
64 ; CHECK: vn %v24, %v24, [[REG]]
75 ; CHECK: vn %v24, %v24, [[REG]]
86 ; CHECK: vn %v24, %v24, [[REG]]
97 ; CHECK: vn %v24, %v24, [[REG]]
108 ; CHECK: vn %v24, %v24, [[REG]]
Dvec-and-01.ll8 ; CHECK: vn %v24, %v26, %v28
17 ; CHECK: vn %v24, %v26, %v28
26 ; CHECK: vn %v24, %v26, %v28
35 ; CHECK: vn %v24, %v26, %v28
/external/llvm/test/CodeGen/SystemZ/
Dvec-and-03.ll9 ; CHECK: vn %v24, %v24, [[REG]]
20 ; CHECK: vn %v24, %v24, [[REG]]
31 ; CHECK: vn %v24, %v24, [[REG]]
42 ; CHECK: vn %v24, %v24, [[REG]]
53 ; CHECK: vn %v24, %v24, [[REG]]
64 ; CHECK: vn %v24, %v24, [[REG]]
75 ; CHECK: vn %v24, %v24, [[REG]]
86 ; CHECK: vn %v24, %v24, [[REG]]
97 ; CHECK: vn %v24, %v24, [[REG]]
108 ; CHECK: vn %v24, %v24, [[REG]]
Dvec-and-01.ll8 ; CHECK: vn %v24, %v26, %v28
17 ; CHECK: vn %v24, %v26, %v28
26 ; CHECK: vn %v24, %v26, %v28
35 ; CHECK: vn %v24, %v26, %v28
/external/brotli/tests/testdata/
Dmonkey1 …z,xvnm.,zxcnv.,xcn.z,vn.zvn.zxcvn.,zxcn.vn.v,znm.,vnzx.,vnzxc.vn.z,vnz.,nv.z,nvmzxc,nvzxcvcnm.,vcz…
/external/tcpdump/
Dprint-nsh.c51 int n, vn; in nsh_print() local
145 for (vn = 0; vn < tlv_len; vn++) { in nsh_print()
148 ND_PRINT((ndo, "\n Value[%02d]: 0x%08x", vn, ctx)); in nsh_print()
/external/Reactive-Extensions/RxCpp/Rx/v2/src/rxcpp/sources/
Drx-iterate.hpp221 auto from(Value0 v0, ValueN... vn) in from() argument
224 std::array<Value0, sizeof...(ValueN) + 1> c{{v0, vn...}}; in from()
246 auto from(Coordination cn, Value0 v0, ValueN... vn) in from() argument
249 std::array<Value0, sizeof...(ValueN) + 1> c{{v0, vn...}}; in from()
316 auto start_with(Observable o, Value0 v0, ValueN... vn) in start_with() argument
317 …-> decltype(from(rxu::value_type_t<Observable>(v0), rxu::value_type_t<Observable>(vn)...).concat(o… in start_with()
318 …return from(rxu::value_type_t<Observable>(v0), rxu::value_type_t<Observable>(vn)...).concat(o… in start_with()
/external/v8/src/arm/
Dassembler-arm.cc3267 int vn, n; in vadd() local
3268 src1.split_code(&vn, &n); in vadd()
3271 emit(cond | 0x1C*B23 | d*B22 | 0x3*B20 | vn*B16 | vd*B12 | 0x5*B9 | B8 | in vadd()
3285 int vn, n; in vadd() local
3286 src1.split_code(&vn, &n); in vadd()
3289 emit(cond | 0x1C * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 | in vadd()
3308 int vn, n; in vsub() local
3309 src1.split_code(&vn, &n); in vsub()
3312 emit(cond | 0x1C*B23 | d*B22 | 0x3*B20 | vn*B16 | vd*B12 | 0x5*B9 | B8 | in vsub()
3326 int vn, n; in vsub() local
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/external/mksh/src/
Dvar.c151 varsearch(struct block *l, struct tbl **vpp, const char *vn, uint32_t h) in varsearch() argument
157 if ((vp = ktsearch(&l->vars, vn, h)) != NULL) in varsearch()
188 char *vn; in array_index_calc() local
190 strndupx(vn, n, p - n, ATEMP); in array_index_calc()
192 varsearch(e->loc, &vp, vn, hash(vn)); in array_index_calc()
193 afree(vn, ATEMP); in array_index_calc()
224 #define vn vname.ro macro
249 vn = array_index_calc(n, &array, &val); in isglobal()
250 h = hash(vn); in isglobal()
251 c = (unsigned char)vn[0]; in isglobal()
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/external/u-boot/net/
Dsntp.h36 uchar vn:3; member
40 uchar vn:3;
/external/llvm/lib/Support/
Dregexec.c113 #define STATEVARS long vn; char *space
116 (m)->vn = 0; }
118 #define SETUP(v) ((v) = &m->space[m->vn++ * m->g->nstates])
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/
Dregexec.c113 #define STATEVARS long vn; char *space
116 (m)->vn = 0; }
118 #define SETUP(v) ((v) = &m->space[m->vn++ * m->g->nstates])
/external/swiftshader/third_party/LLVM/lib/Support/
Dregexec.c113 #define STATEVARS long vn; char *space
116 (m)->vn = 0; }
118 #define SETUP(v) ((v) = &m->space[m->vn++ * m->g->nstates])
/external/swiftshader/third_party/llvm-subzero/lib/Support/
Dregexec.c113 #define STATEVARS long vn; char *space
116 (m)->vn = 0; }
118 #define SETUP(v) ((v) = &m->space[m->vn++ * m->g->nstates])
/external/swiftshader/third_party/llvm-7.0/llvm/test/Other/
Ddebugcounter-newgvn.ll3 ; RUN: opt -S -debug-counter=newgvn-vn-skip=1,newgvn-vn-count=2 -newgvn < %s 2>&1 | FileCheck %s
/external/Reactive-Extensions/RxCpp/Rx/v2/src/rxcpp/operators/
Drx-merge.hpp261 static Result member(Observable&& o, Value0&& v0, ValueN&&... vn) { in member()
262 …return Result(Merge(rxs::from(o.as_dynamic(), v0.as_dynamic(), vn.as_dynamic()...), identity_curre… in member()
276 static Result member(Observable&& o, Coordination&& cn, Value0&& v0, ValueN&&... vn) { in member()
277 …return Result(Merge(rxs::from(o.as_dynamic(), v0.as_dynamic(), vn.as_dynamic()...), std::forward<C… in member()
Drx-start_with.hpp68 static auto member(Observable&& o, Value0&& v0, ValueN&&... vn) in member()
70 auto first = rxs::from(rxu::decay_t<Value0>(v0), rxu::decay_t<ValueN>(vn)...); in member()
Drx-merge_delay_error.hpp275 static Result member(Observable&& o, Value0&& v0, ValueN&&... vn) { in member()
276 …return Result(Merge(rxs::from(o.as_dynamic(), v0.as_dynamic(), vn.as_dynamic()...), identity_curre… in member()
290 static Result member(Observable&& o, Coordination&& cn, Value0&& v0, ValueN&&... vn) { in member()
291 …return Result(Merge(rxs::from(o.as_dynamic(), v0.as_dynamic(), vn.as_dynamic()...), std::forward<C… in member()

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