| /external/libvpx/libvpx/vp8/common/mips/msa/ |
| D | idct_msa.c | 90 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in idct4x4_addblk_msa() local
100 VP8_IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3); in idct4x4_addblk_msa()
101 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in idct4x4_addblk_msa()
102 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in idct4x4_addblk_msa()
108 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in idct4x4_addblk_msa()
183 v4i32 hz0_w, hz1_w, hz2_w, hz3_w, vt0, vt1, vt2, vt3, res0, res1, res2, res3; in dequant_idct4x4_addblk_msa() local
196 VP8_IDCT_1D_W(hz0_w, hz1_w, hz2_w, hz3_w, vt0, vt1, vt2, vt3); in dequant_idct4x4_addblk_msa()
197 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in dequant_idct4x4_addblk_msa()
198 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in dequant_idct4x4_addblk_msa()
204 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in dequant_idct4x4_addblk_msa()
[all …]
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 1392 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld1() argument
1395 ld1(vt, vt2, vt3, src); in Ld1()
1397 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld1() argument
1400 ld1(vt, vt2, vt3, vt4, src); in Ld1()
1423 void Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld3() argument
1426 ld3(vt, vt2, vt3, src); in Ld3()
1428 void Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld3() argument
1431 ld3(vt, vt2, vt3, lane, src); in Ld3()
1433 void Ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld3r() argument
1436 ld3r(vt, vt2, vt3, src); in Ld3r()
[all …]
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| D | assembler-arm64.cc | 2742 const VRegister& vt3, const MemOperand& src) { in ld1() argument
2744 USE(vt3); in ld1()
2745 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld1()
2746 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld1()
2751 const VRegister& vt3, const VRegister& vt4, in ld1() argument
2754 USE(vt3); in ld1()
2756 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld1()
2757 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
2786 const VRegister& vt3, const MemOperand& src) { in ld3() argument
2788 USE(vt3); in ld3()
[all …]
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| D | assembler-arm64.h | 2021 void st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2025 void st1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2039 void st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2043 void st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2047 void st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2051 void st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2632 void ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2636 void ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2656 void ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
2660 void ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
[all …]
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 1915 const VRegister& vt3, in ld1() argument
1917 USE(vt2, vt3); in ld1()
1919 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3)); in ld1()
1920 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3)); in ld1()
1927 const VRegister& vt3, in ld1() argument
1930 USE(vt2, vt3, vt4); in ld1()
1932 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4)); in ld1()
1933 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
1974 const VRegister& vt3, in ld3() argument
1976 USE(vt2, vt3); in ld3()
[all …]
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| D | macro-assembler-aarch64.h | 2965 const VRegister& vt3, in Ld1() argument
2969 ld1(vt, vt2, vt3, src); in Ld1()
2973 const VRegister& vt3, in Ld1() argument
2978 ld1(vt, vt2, vt3, vt4, src); in Ld1()
3010 const VRegister& vt3, in Ld3() argument
3014 ld3(vt, vt2, vt3, src); in Ld3()
3018 const VRegister& vt3, in Ld3() argument
3023 ld3(vt, vt2, vt3, lane, src); in Ld3()
3027 const VRegister& vt3, in Ld3r() argument
3031 ld3r(vt, vt2, vt3, src); in Ld3r()
[all …]
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| D | assembler-aarch64.h | 2793 const VRegister& vt3,
2799 const VRegister& vt3,
2824 const VRegister& vt3,
2830 const VRegister& vt3,
2837 const VRegister& vt3,
2843 const VRegister& vt3,
2850 const VRegister& vt3,
2858 const VRegister& vt3,
2997 const VRegister& vt3,
3003 const VRegister& vt3,
[all …]
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| /external/llvm/test/Transforms/WholeProgramDevirt/ |
| D | unique-retval.ll | 8 @vt3 = constant [1 x i8*] [i8* bitcast (i1 (i8*)* @vf1 to i8*)], !type !0, !type !1
30 ; CHECK: [[RES1:%[^ ]*]] = icmp eq i8* [[VT1]], bitcast ([1 x i8*]* @vt3 to i8*)
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| D | virtual-const-prop-end.ll | 22 @vt3 = constant [4 x i8*] [
38 ; CHECK: @vt3 = alias [4 x i8*], getelementptr inbounds ({ [0 x i8], [4 x i8*], [8 x i8] }, { [0 x …
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| D | virtual-const-prop-check.ll | 26 @vt3 = constant [3 x i8*] [
48 ; CHECK: @vt3 = alias [3 x i8*], getelementptr inbounds ({ [8 x i8], [3 x i8*], [0 x i8] }, { [8 x …
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| D | virtual-const-prop-begin.ll | 21 @vt3 = constant [3 x i8*] [
43 ; CHECK: @vt3 = alias [3 x i8*], getelementptr inbounds ({ [8 x i8], [3 x i8*], [0 x i8] }, { [8 x …
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/WholeProgramDevirt/ |
| D | unique-retval.ll | 8 @vt3 = constant [1 x i8*] [i8* bitcast (i1 (i8*)* @vf1 to i8*)], !type !0, !type !1
31 ; CHECK: [[RES1:%[^ ]*]] = icmp eq i8* [[VT1]], bitcast ([1 x i8*]* @vt3 to i8*)
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| D | virtual-const-prop-end.ll | 22 @vt3 = constant [4 x i8*] [
38 ; CHECK: @vt3 = alias [4 x i8*], getelementptr inbounds ({ [0 x i8], [4 x i8*], [8 x i8] }, { [0 x …
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| D | virtual-const-prop-begin.ll | 21 @vt3 = constant [3 x i8*] [
43 ; CHECK: @vt3 = alias [3 x i8*], getelementptr inbounds ({ [8 x i8], [3 x i8*], [0 x i8] }, { [8 x …
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| D | virtual-const-prop-check.ll | 32 @vt3 = constant [3 x i8*] [
54 ; CHECK: @vt3 = alias [3 x i8*], getelementptr inbounds ({ [8 x i8], [3 x i8*], [0 x i8] }, { [8 x …
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| D | export-single-impl.ll | 69 @vt3 = constant void (i8*)* @vf3, !type !2
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| D | vcp-too-wide-ints.ll | 8 @vt3 = constant [1 x i8*] [i8* bitcast (i128 (i8*, i64)* @vf3 to i8*)], !type !1
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| /external/clang/test/SemaObjCXX/ |
| D | decltype.mm | 23 decltype(self.bar)::value_type vt3;
|
| /external/webp/src/dsp/ |
| D | enc_msa.c | 47 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ITransformOne() local
57 IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3); in ITransformOne()
58 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in ITransformOne()
59 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in ITransformOne()
65 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in ITransformOne()
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| D | dec_msa.c | 45 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in TransformOne() local
55 IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3); in TransformOne()
56 SRARI_W4_SW(vt0, vt1, vt2, vt3, 3); in TransformOne()
57 TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3); in TransformOne()
63 ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3); in TransformOne()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2424 const VRegister& vt3,
2442 const VRegister& vt3,
2490 const VRegister& vt3,
2501 const VRegister& vt3,
2511 const VRegister& vt3,
2521 const VRegister& vt3,
2533 const VRegister& vt3,
2544 const VRegister& vt3,
3490 const VRegister& vt3,
3508 const VRegister& vt3,
[all …]
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