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Searched refs:BaseOffs (Results 1 – 25 of 45) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/
DAddrModeMatcher.cpp39 if (BaseOffs) in print()
40 OS << (NeedPlus ? " + " : "") << BaseOffs, NeedPlus = true; in print()
104 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; in MatchScaledValue()
249 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
255 AddrMode.BaseOffs -= ConstantOffset; in MatchOperationAddr()
264 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
289 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
313 AddrMode.BaseOffs += CI->getSExtValue(); in MatchAddr()
316 AddrMode.BaseOffs -= CI->getSExtValue(); in MatchAddr()
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp377 if (AM.BaseOffs != 0) { in print()
379 OS << AM.BaseOffs; in print()
839 int64_t Offset = (uint64_t)*I + F.AM.BaseOffs; in RateFormula()
1188 return !AM.BaseGV && AM.BaseOffs == 0 && AM.Scale <= 1; in isLegalUse()
1197 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0) in isLegalUse()
1207 if (AM.BaseOffs != 0) { in isLegalUse()
1208 if (TLI) return TLI->isLegalICmpImmediate(-(uint64_t)AM.BaseOffs); in isLegalUse()
1216 return !AM.BaseGV && AM.Scale == 0 && AM.BaseOffs == 0; in isLegalUse()
1231 if (((int64_t)((uint64_t)AM.BaseOffs + MinOffset) > AM.BaseOffs) != in isLegalUse()
1234 AM.BaseOffs = (uint64_t)AM.BaseOffs + MinOffset; in isLegalUse()
[all …]
DCodeGenPrepare.cpp878 if (AddrMode.BaseOffs) { in OptimizeMemoryInst()
879 Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs); in OptimizeMemoryInst()
/external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/
DAddrModeMatcher.h45 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
/external/swiftshader/third_party/LLVM/lib/Analysis/
DBasicAliasAnalysis.cpp259 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, in DecomposeGEPExpression() argument
265 BaseOffs = 0; in DecomposeGEPExpression()
326 BaseOffs += TD->getStructLayout(STy)->getElementOffset(FieldNo); in DecomposeGEPExpression()
333 BaseOffs += TD->getTypeAllocSize(*GTI)*CIdx->getSExtValue(); in DecomposeGEPExpression()
353 BaseOffs += IndexOffset.getSExtValue()*Scale; in DecomposeGEPExpression()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp1560 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1566 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1573 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1576 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1581 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1584 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1588 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1591 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DCodeGenPrepare.cpp1942 if (BaseOffs != other.BaseOffs) in compare()
1964 return !BaseOffs && !Scale && !(BaseGV && BaseReg); in isTrivial()
1978 return ConstantInt::get(IntPtrTy, BaseOffs); in GetFieldAsValue()
2015 BaseOffs = 0; in SetCombinedField()
2041 if (BaseOffs) { in print()
2043 << BaseOffs; in print()
3221 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; in matchScaledValue()
3862 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
3893 AddrMode.BaseOffs -= ConstantOffset; in matchOperationAddr()
3902 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
[all …]
DTargetLoweringBase.cpp1589 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1601 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1606 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp2092 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && in operator ==()
2114 if (BaseOffs) { in print()
2116 << BaseOffs; in print()
2701 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; in matchScaledValue()
3264 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
3271 AddrMode.BaseOffs -= ConstantOffset; in matchOperationAddr()
3280 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
3305 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
3388 AddrMode.BaseOffs += CI->getSExtValue(); in matchAddr()
3391 AddrMode.BaseOffs -= CI->getSExtValue(); in matchAddr()
[all …]
DTargetLoweringBase.cpp1783 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1795 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1800 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1891 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1896 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1903 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1906 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1911 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1914 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1918 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1921 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1910 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1915 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1922 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1925 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1930 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1933 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1937 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1940 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUPerfHintAnalysis.cpp249 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
DSIISelLowering.cpp872 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
879 return isUInt<12>(AM.BaseOffs) && AM.Scale == 0; in isLegalFlatAddressingMode()
884 return isInt<13>(AM.BaseOffs) && AM.Scale == 0; in isLegalGlobalAddressingMode()
912 if (!isUInt<12>(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
952 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
964 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
969 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
973 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
994 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
6220 AM.BaseOffs = Offset.getSExtValue(); in performSHLPtrCombine()
/external/llvm/include/llvm/CodeGen/
DBasicTTIImpl.h131 AM.BaseOffs = BaseOffset; in isLegalAddressingMode()
141 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp295 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1); in isLegalFlatAddressingMode()
308 if (!isUInt<12>(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
360 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
372 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
377 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
381 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
404 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h1528 int64_t BaseOffs; member
1531 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DBasicTTIImpl.h170 AM.BaseOffs = BaseOffset;
196 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
/external/llvm/include/llvm/Target/
DTargetLowering.h1592 int64_t BaseOffs; member
1595 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp225 if (AM.BaseOffs < 0) return false; in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3189 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
3201 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
3206 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp404 if (AM.BaseOffs < 0) return false; in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp3251 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0) in isLegalAddressingMode()
3255 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs)) in isLegalAddressingMode()
3259 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 1 && AM.BaseOffs ==0) in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp5666 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
5678 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
5683 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp172 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()

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