| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | fcopysign-f32-f64.ll | 19 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
20 ; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
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| /external/llvm/test/CodeGen/Mips/ |
| D | fcopysign-f32-f64.ll | 19 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
20 ; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 117 def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
198 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
200 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 72 case Mips::DSRL: in LowerLargeShift()
197 case Mips::DSRL: in encodeInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 80 case Mips::DSRL: in LowerLargeShift()
166 case Mips::DSRL: in encodeInstruction()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 543 DSRL = ((7U << 3) + 2), enumerator
1321 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(DSRL) |
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| D | disasm-mips64.cc | 1464 case DSRL: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2176 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL); in dsrl()
2188 | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL; in drotr()
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| D | simulator-mips64.cc | 3717 case DSRL: in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 143 def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
588 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 495 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 147 #define DSRL (HI(0) | LO(58)) macro
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 161 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl,
760 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>,
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3620 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
3638 SecondShift = Mips::DSRL; in expandDRotationImm()
3643 FirstShift = Mips::DSRL; in expandDRotationImm()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4640 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
4658 SecondShift = Mips::DSRL; in expandDRotationImm()
4663 FirstShift = Mips::DSRL; in expandDRotationImm()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 640 1107318355U, // DSRL
2354 0U, // DSRL
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| D | MipsGenDisassemblerTables.inc | 4149 /* 267 */ MCD_OPC_Decode, 239, 4, 232, 1, // Opcode: DSRL
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1299 UINT64_C(58), // DSRL
4676 case Mips::DSRL:
9025 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRL = 1286
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| D | MipsGenAsmWriter.inc | 2514 268458180U, // DSRL
5145 12U, // DSRL
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| D | MipsGenGlobalISel.inc | 12330 …// (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{…
12336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
12751 …:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Op…
12752 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
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| D | MipsGenFastISel.inc | 3756 return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
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| D | MipsGenAsmMatcher.inc | 6117 …{ 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Featur…
6119 …{ 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Featur…
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| D | MipsGenDAGISel.inc | 15610 /* 28624*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRL), 0,
15613 … // Dst: (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
20813 /* 38523*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRL), 0,
20816 // Dst: (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
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| D | MipsGenInstrInfo.inc | 1301 DSRL = 1286,
5346 …286, 3, 1, 4, 121, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1286 = DSRL
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| D | MipsGenDisassemblerTables.inc | 6877 /* 376 */ MCD::OPC_Decode, 134, 10, 236, 2, // Opcode: DSRL
|