| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 207 return push_inst(compiler, DSRL32 | T(dst) | D(dst) | SH_IMM(0), DR(dst)); in emit_single_op()
230 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_… in emit_single_op()
295 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), … in emit_single_op()
428 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OTHER_FLAG) | DA(OTHER_FLAG) | SH_IMM(31), … in emit_single_op()
495 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 148 #define DSRL32 (HI(0) | LO(62)) macro
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 120 def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 546 DSRL32 = ((7U << 3) + 6), enumerator
1322 FunctionFieldToBitNumber(DSRL32) | FunctionFieldToBitNumber(SRA) |
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| D | disasm-mips64.cc | 1471 case DSRL32: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2195 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL32; in drotr32()
2223 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL32); in dsrl32()
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| D | simulator-mips64.cc | 3733 case DSRL32: in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 73 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
3630 SecondShift = Mips::DSRL32; in expandDRotationImm()
3634 SecondShift = Mips::DSRL32; in expandDRotationImm()
3647 FirstShift = Mips::DSRL32; in expandDRotationImm()
3651 FirstShift = Mips::DSRL32; in expandDRotationImm()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 81 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2724 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
4650 SecondShift = Mips::DSRL32; in expandDRotationImm()
4654 SecondShift = Mips::DSRL32; in expandDRotationImm()
4667 FirstShift = Mips::DSRL32; in expandDRotationImm()
4671 FirstShift = Mips::DSRL32; in expandDRotationImm()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 158 def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 175 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 641 1107312825U, // DSRL32
2355 0U, // DSRL32
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| D | MipsGenDisassemblerTables.inc | 4165 /* 338 */ MCD_OPC_Decode, 240, 4, 232, 1, // Opcode: DSRL32
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1300 UINT64_C(62), // DSRL32
4677 case Mips::DSRL32:
9026 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRL32 = 1287
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| D | MipsGenAsmWriter.inc | 2515 268452095U, // DSRL32
5146 4U, // DSRL32
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| D | MipsGenAsmMatcher.inc | 6120 …{ 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Fe…
6121 …{ 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Fe…
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| D | MipsGenInstrInfo.inc | 1302 DSRL32 = 1287,
5347 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1287 = DSRL32
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| D | MipsGenDisassemblerTables.inc | 6893 /* 458 */ MCD::OPC_Decode, 135, 10, 236, 2, // Opcode: DSRL32
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