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Searched refs:FGETSIGN (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h245 FGETSIGN, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h258 FGETSIGN, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h292 FGETSIGN, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dmovmsk.ll98 ; FIXME: This should also use movmskps; we don't form the FGETSIGN node
/external/llvm/test/CodeGen/X86/
Dmovmsk.ll98 ; FIXME: This should also use movmskps; we don't form the FGETSIGN node
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp204 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
DTargetLowering.cpp1114 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); in SimplifyDemandedBits()
1115 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
1122 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); in SimplifyDemandedBits()
DSelectionDAG.cpp2329 case ISD::FGETSIGN: in computeKnownBits()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp243 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
DTargetLowering.cpp1187 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); in SimplifyDemandedBits()
1188 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
1196 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); in SimplifyDemandedBits()
DSelectionDAG.cpp2723 case ISD::FGETSIGN: in computeKnownBits()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp565 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); in TargetLowering()
1789 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); in SimplifyDemandedBits()
1790 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
1795 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); in SimplifyDemandedBits()
DSelectionDAG.cpp1952 case ISD::FGETSIGN: in ComputeMaskedBits()
6000 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp598 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp866 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSelectionDAG.td371 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td439 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td421 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp567 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
568 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
10417 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp681 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
734 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp884 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
936 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp507 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
508 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
21706 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp543 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
544 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
25328 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp660 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp742 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()