| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 794 ISDs.push_back(ISD::FRINT); in getIntrinsicInstrCost()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 559 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 331 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
388 Opcode = ISD::FRINT; break; in mightUseCTR()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 305 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
360 Opcode = ISD::FRINT; break; in mightUseCTR()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedM1.td | 255 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>;
316 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>;
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| D | AArch64SchedA57.td | 486 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
488 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
559 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 186 case ISD::FRINT: in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 88 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
868 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 85 case ISD::FRINT: in ScalarizeVectorResult()
462 case ISD::FRINT: in SplitVectorResult()
1309 case ISD::FRINT: in WidenVectorResult()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 490 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
492 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
563 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
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| D | AArch64SchedFalkorDetails.td | 593 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
618 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1124 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
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| D | AArch64SchedExynosM1.td | 468 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>;
566 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>;
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| D | AArch64SchedExynosM3.td | 533 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
643 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
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| D | AArch64SchedThunderX2T99.td | 1186 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1407 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1410 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 165 case ISD::FRINT: return "frint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 100 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1037 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
1880 case ISD::FRINT: in PromoteFloatResult()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 244 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
279 setOperationAction(ISD::FRINT, MVT::f64, Custom); in AMDGPUTargetLowering()
422 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
715 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
1723 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 191 case ISD::FRINT: return "frint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 100 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1091 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
1898 case ISD::FRINT: in PromoteFloatResult()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 311 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
462 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
555 case ISD::FRINT: in fnegFoldsIntoOp()
1135 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
2073 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
3596 case ISD::FRINT: in performFNegCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 94 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 816 FRINT = (6U << 17), enumerator
|