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Searched refs:OpNode (Results 1 – 25 of 96) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrAVX512.td1354 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1361 (OpNode (_.VT _.RC:$src1),
1369 (OpNode (_.VT _.RC:$src1),
1409 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1418 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1432 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1437 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1442 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1450 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1457 (OpNode (_.VT _.RC:$src1),
[all …]
DX86InstrXOP.td86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
98 (vt128 (OpNode (vt128 VR128:$src1),
105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
125 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
131 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
136 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
180 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
187 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
195 (vt128 (OpNode (vt128 VR128:$src1),
[all …]
DX86InstrFMA.td145 SDPatternOperator OpNode = null_frag> {
151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
195 SDNode OpNode, RegisterClass RC,
199 OpNode>;
225 SDNode OpNode> {
227 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", OpNode,
232 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", OpNode,
268 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
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DX86InstrFPStack.td127 multiclass FPBinary_rr<SDNode OpNode> {
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
147 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
149 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
154 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
156 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
161 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1327 SDNode OpNode>
1329 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1332 SDNode OpNode>
1334 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1340 SDNode OpNode, SDNode OpNode_setflags> {
1341 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1345 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1364 SDPatternOperator OpNode>
1367 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1380 SDPatternOperator OpNode>
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrAVX512.td1259 X86VectorVTInfo _, SDPatternOperator OpNode,
1265 (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX,
1270 X86VectorVTInfo _, SDPatternOperator OpNode,
1280 def : Pat <(_.VT (OpNode SrcRC:$src)),
1284 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0),
1288 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV),
1294 AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
1298 OpNode, SrcRC, Subreg>, EVEX_V512;
1301 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1303 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
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DX86InstrFMA.td179 SDPatternOperator OpNode,
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
200 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
220 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
236 (OpNode (load addr:$src3), RC:$src1, RC:$src2))]>,
243 SDNode OpNode, RegisterClass RC,
246 x86memop, RC, OpNode, sched>;
248 x86memop, RC, OpNode, sched>;
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DX86InstrFPStack.td127 multiclass FPBinary_rr<SDNode OpNode> {
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
148 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
150 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
155 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
157 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
162 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1624 SDPatternOperator OpNode>
1627 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
1685 SDNode OpNode>
1687 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1690 SDNode OpNode>
1692 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1698 SDNode OpNode, SDNode OpNode_setflags> {
1699 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1703 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1722 SDPatternOperator OpNode>
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/external/tensorflow/tensorflow/core/profiler/internal/
Dtfprof_op.h55 int64 SearchRoot(const std::vector<OpNode*> nodes,
66 string FormatNode(OpNode* node, OpNode* root, const Options& opts) const;
70 std::unique_ptr<OpNode> root_;
71 std::map<string, std::unique_ptr<OpNode>> cnodes_map_;
Dtfprof_op.cc97 std::unique_ptr<OpNode>(new OpNode(tn.second.get())); in Build()
102 root_.reset(new OpNode(tfcnodes_map_[kTFProfRoot].get())); in Build()
125 std::vector<OpNode*> nodes; in ShowInternal()
134 OpNode* pre = nullptr; in ShowInternal()
135 std::vector<OpNode*> account_nodes; in ShowInternal()
150 std::vector<OpNode*> show_nodes; in ShowInternal()
153 OpNode* n = account_nodes[i]; in ShowInternal()
178 for (OpNode* node : show_nodes) { in ShowInternal()
195 int64 TFOp::SearchRoot(const std::vector<OpNode*> nodes, in SearchRoot()
225 string TFOp::FormatNode(OpNode* node, OpNode* root, const Options& opts) const { in FormatNode()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h80 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
82 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
84 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td169 multiclass I3<string OpcStr, SDNode OpNode> {
173 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
177 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
181 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
185 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
189 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
193 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
198 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
202 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
206 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td159 multiclass I3<string OpcStr, SDNode OpNode> {
163 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
167 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
171 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
175 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
179 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
183 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
188 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
192 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
196 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
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/external/tensorflow/tensorflow/lite/delegates/flex/
Dkernel.cc54 struct OpNode;
59 OpNode* node;
176 class OpNode { class
178 OpNode(const TfLiteIntArray* inputs, const TfLiteIntArray* outputs) in OpNode() function in tflite::flex::kernel::OpNode
180 ~OpNode() { in ~OpNode()
315 OpNode(const OpNode&) = delete;
316 OpNode& operator=(const OpNode&) = delete;
335 OpNode* node_data) { in ExecuteFlexOp()
364 std::vector<std::unique_ptr<OpNode>> nodes;
404 op_data->nodes.emplace_back(new OpNode(node->inputs, node->outputs)); in Init()
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/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
265 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
276 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
281 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
287 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
298 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
309 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
[all …]
DMipsInstrFPU.td105 SDPatternOperator OpNode= null_frag> :
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
114 SDPatternOperator OpNode = null_frag> {
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
129 SDPatternOperator OpNode= null_frag> {
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td260 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
266 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
271 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
277 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
282 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
288 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
293 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
299 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
304 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
310 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
[all …]
DMipsInstrFPU.td110 SDPatternOperator OpNode= null_frag> :
113 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
119 SDPatternOperator OpNode = null_frag> {
120 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
121 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
127 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
134 SDPatternOperator OpNode= null_frag> {
135 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
137 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFSL.td13 class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
16 [(set GPR:$dst, (OpNode immZExt4:$b))],IIC_FSLg>
29 class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
32 [(set GPR:$dst, (OpNode GPR:$b))], IIC_FSLg>
45 class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
48 [(OpNode GPR:$v, immZExt4:$b)], IIC_FSLp>
61 class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
64 [(OpNode GPR:$v, GPR:$b)], IIC_FSLp>
77 class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
80 [(OpNode immZExt4:$b)], IIC_FSLp>
[all …]
DMBlazeInstrFPU.td21 class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>;
26 class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
31 class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>;
36 class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
41 class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
45 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
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/external/skia/src/gpu/
DGrAuditTrail.cpp48 OpNode* opNode = new OpNode(proxyID); in addOp()
60 OpNode& consumerOp = *fOpList[index]; in opsCombined()
67 OpNode& consumedOp = *fOpList[consumedIndex]; in opsCombined()
90 const OpNode* bn = fOpList[opListID].get(); in copyOutFromOpList()
194 void GrAuditTrail::OpNode::toJson(SkJSONWriter& writer) const { in toJson()
/external/skqp/src/gpu/
DGrAuditTrail.cpp48 OpNode* opNode = new OpNode(proxyID); in addOp()
60 OpNode& consumerOp = *fOpList[index]; in opsCombined()
67 OpNode& consumedOp = *fOpList[consumedIndex]; in opsCombined()
90 const OpNode* bn = fOpList[opListID].get(); in copyOutFromOpList()
194 void GrAuditTrail::OpNode::toJson(SkJSONWriter& writer) const { in toJson()
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td140 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
159 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
178 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
179 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
180 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
316 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
317 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
344 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
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