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Searched refs:RegVT (Results 1 – 25 of 44) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXISelLowering.cpp238 EVT RegVT = Ins[i].VT; in LowerFormalArguments() local
239 TargetRegisterClass* TRC = getRegClassFor(RegVT); in LowerFormalArguments()
245 SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain, in LowerFormalArguments()
299 EVT RegVT = Outs[i].VT; in LowerReturn() local
303 if (RegVT == MVT::i1) { in LowerReturn()
306 else if (RegVT == MVT::i16) { in LowerReturn()
309 else if (RegVT == MVT::i32) { in LowerReturn()
312 else if (RegVT == MVT::i64) { in LowerReturn()
315 else if (RegVT == MVT::f32) { in LowerReturn()
318 else if (RegVT == MVT::f64) { in LowerReturn()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2ISelLowering.cpp110 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
112 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
117 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
130 DAG.getNode(Opcode, DL, RegVT, ArgValue, DAG.getValueType(ValVT)); in LowerFormalArguments()
135 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
136 (RegVT == MVT::i64 && ValVT == MVT::f64)) in LowerFormalArguments()
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp241 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
243 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
245 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
248 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DCallingConvLower.cpp258 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
260 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
262 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
265 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1104 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1105 if (RegVT == MVT::i8 || RegVT == MVT::i16 || in LowerFormalArguments()
1106 RegVT == MVT::i32 || RegVT == MVT::f32) { in LowerFormalArguments()
1110 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1111 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) { in LowerFormalArguments()
1115 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1118 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1119 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1123 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1125 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
[all …]
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp174 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
175 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
178 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
184 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp721 MVT RegVT = VA.getLocVT(); in LowerCall() local
729 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
732 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
735 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
896 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
900 if (RegVT == MVT::i32) in LowerFormalArguments()
902 else if (RegVT == MVT::f32) in LowerFormalArguments()
910 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
923 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, in LowerFormalArguments()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp185 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
189 assert(RC->hasType(RegVT) && "Unexpected regclass in CCState"); in LowerFormalArguments()
193 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
199 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
202 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
229 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
233 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRISelLowering.cpp1062 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1064 if (RegVT == MVT::i8) { in LowerFormalArguments()
1066 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1073 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1090 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1095 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1191 EVT RegVT = VA.getLocVT(); in LowerCall() local
1201 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1204 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1207 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp326 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
327 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
332 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
346 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
349 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCISelLowering.cpp486 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
487 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
490 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
496 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp436 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
437 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
442 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp444 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
445 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
455 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
469 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp2277 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
2281 if (RegVT == MVT::i32) in LowerFormalArguments()
2283 else if (RegVT == MVT::i64) in LowerFormalArguments()
2285 else if (RegVT == MVT::f32) in LowerFormalArguments()
2287 else if (RegVT == MVT::f64) in LowerFormalArguments()
2295 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
2307 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, in LowerFormalArguments()
2314 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) in LowerFormalArguments()
2316 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { in LowerFormalArguments()
2319 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp618 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
619 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
624 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
631 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
637 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
640 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.h275 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E), in BitTestBlock()
281 EVT RegVT; member
DSelectionDAGBuilder.cpp1707 B.RegVT = VT; in visitBitTestHeader()
1741 EVT VT = BB.RegVT; in visitBitTestCase()
5739 EVT RegVT = *PhysReg.second->vt_begin(); in GetRegistersForValue() local
5740 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in GetRegistersForValue()
5742 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
5743 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
5744 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
5749 RegVT = EVT::getIntegerVT(Context, in GetRegistersForValue()
5752 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
5753 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
[all …]
DLegalizeDAG.cpp406 EVT RegVT = in ExpandUnalignedStore() local
411 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedStore()
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in ExpandUnalignedStore()
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, in ExpandUnalignedStore()
450 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); in ExpandUnalignedLoad() local
523 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in ExpandUnalignedLoad()
537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, in ExpandUnalignedLoad()
554 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in ExpandUnalignedLoad()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3207 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
3208 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
3275 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
3277 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
3281 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
3296 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, in expandUnalignedLoad()
3315 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
3432 MVT RegVT = in expandUnalignedStore() local
3438 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
3442 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in expandUnalignedStore()
[all …]
DSelectionDAGBuilder.h291 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
297 MVT RegVT; member
DSelectionDAGBuilder.cpp2170 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2171 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2200 MVT VT = BB.RegVT; in visitBitTestCase()
6486 MVT RegVT = *PhysReg.second->vt_begin(); in GetRegistersForValue() local
6487 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) { in GetRegistersForValue()
6489 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
6490 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
6491 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
6496 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); in GetRegistersForValue()
6498 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp731 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
733 RegVT = VA.getValVT(); in LowerFormalArguments()
735 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
737 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
743 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
744 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
745 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
746 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
750 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
752 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3914 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
3915 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
4014 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
4016 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
4020 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
4036 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), in expandUnalignedLoad()
4054 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
4165 MVT RegVT = in expandUnalignedStore() local
4171 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
4175 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in expandUnalignedStore()
[all …]

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